1 /*
2 * Copyright (C) 2013 Emilio López <emilio@elopez.com.ar>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Adjustable factor-based clock implementation
9 */
10
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/module.h>
16 #include <linux/of_address.h>
17 #include <linux/slab.h>
18 #include <linux/string.h>
19
20 #include "clk-factors.h"
21
22 /*
23 * DOC: basic adjustable factor-based clock
24 *
25 * Traits of this clock:
26 * prepare - clk_prepare only ensures that parents are prepared
27 * enable - clk_enable only ensures that parents are enabled
28 * rate - rate is adjustable.
29 * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
30 * parent - fixed parent. No clk_set_parent support
31 */
32
33 #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
34
35 #define FACTORS_MAX_PARENTS 5
36
37 #define SETMASK(len, pos) (((1U << (len)) - 1) << (pos))
38 #define CLRMASK(len, pos) (~(SETMASK(len, pos)))
39 #define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit))
40
41 #define FACTOR_SET(bit, len, reg, val) \
42 (((reg) & CLRMASK(len, bit)) | (val << (bit)))
43
clk_factors_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)44 static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
45 unsigned long parent_rate)
46 {
47 u8 n = 1, k = 0, p = 0, m = 0;
48 u32 reg;
49 unsigned long rate;
50 struct clk_factors *factors = to_clk_factors(hw);
51 struct clk_factors_config *config = factors->config;
52
53 /* Fetch the register value */
54 reg = readl(factors->reg);
55
56 /* Get each individual factor if applicable */
57 if (config->nwidth != SUNXI_FACTORS_NOT_APPLICABLE)
58 n = FACTOR_GET(config->nshift, config->nwidth, reg);
59 if (config->kwidth != SUNXI_FACTORS_NOT_APPLICABLE)
60 k = FACTOR_GET(config->kshift, config->kwidth, reg);
61 if (config->mwidth != SUNXI_FACTORS_NOT_APPLICABLE)
62 m = FACTOR_GET(config->mshift, config->mwidth, reg);
63 if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE)
64 p = FACTOR_GET(config->pshift, config->pwidth, reg);
65
66 /* Calculate the rate */
67 rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1);
68
69 return rate;
70 }
71
clk_factors_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)72 static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
73 unsigned long *parent_rate)
74 {
75 struct clk_factors *factors = to_clk_factors(hw);
76 factors->get_factors((u32 *)&rate, (u32)*parent_rate,
77 NULL, NULL, NULL, NULL);
78
79 return rate;
80 }
81
clk_factors_determine_rate(struct clk_hw * hw,unsigned long rate,unsigned long min_rate,unsigned long max_rate,unsigned long * best_parent_rate,struct clk_hw ** best_parent_p)82 static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
83 unsigned long min_rate,
84 unsigned long max_rate,
85 unsigned long *best_parent_rate,
86 struct clk_hw **best_parent_p)
87 {
88 struct clk *clk = hw->clk, *parent, *best_parent = NULL;
89 int i, num_parents;
90 unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
91
92 /* find the parent that can help provide the fastest rate <= rate */
93 num_parents = __clk_get_num_parents(clk);
94 for (i = 0; i < num_parents; i++) {
95 parent = clk_get_parent_by_index(clk, i);
96 if (!parent)
97 continue;
98 if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
99 parent_rate = __clk_round_rate(parent, rate);
100 else
101 parent_rate = __clk_get_rate(parent);
102
103 child_rate = clk_factors_round_rate(hw, rate, &parent_rate);
104
105 if (child_rate <= rate && child_rate > best_child_rate) {
106 best_parent = parent;
107 best = parent_rate;
108 best_child_rate = child_rate;
109 }
110 }
111
112 if (best_parent)
113 *best_parent_p = __clk_get_hw(best_parent);
114 *best_parent_rate = best;
115
116 return best_child_rate;
117 }
118
clk_factors_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)119 static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
120 unsigned long parent_rate)
121 {
122 u8 n = 0, k = 0, m = 0, p = 0;
123 u32 reg;
124 struct clk_factors *factors = to_clk_factors(hw);
125 struct clk_factors_config *config = factors->config;
126 unsigned long flags = 0;
127
128 factors->get_factors((u32 *)&rate, (u32)parent_rate, &n, &k, &m, &p);
129
130 if (factors->lock)
131 spin_lock_irqsave(factors->lock, flags);
132
133 /* Fetch the register value */
134 reg = readl(factors->reg);
135
136 /* Set up the new factors - macros do not do anything if width is 0 */
137 reg = FACTOR_SET(config->nshift, config->nwidth, reg, n);
138 reg = FACTOR_SET(config->kshift, config->kwidth, reg, k);
139 reg = FACTOR_SET(config->mshift, config->mwidth, reg, m);
140 reg = FACTOR_SET(config->pshift, config->pwidth, reg, p);
141
142 /* Apply them now */
143 writel(reg, factors->reg);
144
145 /* delay 500us so pll stabilizes */
146 __delay((rate >> 20) * 500 / 2);
147
148 if (factors->lock)
149 spin_unlock_irqrestore(factors->lock, flags);
150
151 return 0;
152 }
153
154 static const struct clk_ops clk_factors_ops = {
155 .determine_rate = clk_factors_determine_rate,
156 .recalc_rate = clk_factors_recalc_rate,
157 .round_rate = clk_factors_round_rate,
158 .set_rate = clk_factors_set_rate,
159 };
160
sunxi_factors_register(struct device_node * node,const struct factors_data * data,spinlock_t * lock,void __iomem * reg)161 struct clk *sunxi_factors_register(struct device_node *node,
162 const struct factors_data *data,
163 spinlock_t *lock,
164 void __iomem *reg)
165 {
166 struct clk *clk;
167 struct clk_factors *factors;
168 struct clk_gate *gate = NULL;
169 struct clk_mux *mux = NULL;
170 struct clk_hw *gate_hw = NULL;
171 struct clk_hw *mux_hw = NULL;
172 const char *clk_name = node->name;
173 const char *parents[FACTORS_MAX_PARENTS];
174 int i = 0;
175
176 /* if we have a mux, we will have >1 parents */
177 while (i < FACTORS_MAX_PARENTS &&
178 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
179 i++;
180
181 /*
182 * some factor clocks, such as pll5 and pll6, may have multiple
183 * outputs, and have their name designated in factors_data
184 */
185 if (data->name)
186 clk_name = data->name;
187 else
188 of_property_read_string(node, "clock-output-names", &clk_name);
189
190 factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
191 if (!factors)
192 return NULL;
193
194 /* set up factors properties */
195 factors->reg = reg;
196 factors->config = data->table;
197 factors->get_factors = data->getter;
198 factors->lock = lock;
199
200 /* Add a gate if this factor clock can be gated */
201 if (data->enable) {
202 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
203 if (!gate) {
204 kfree(factors);
205 return NULL;
206 }
207
208 /* set up gate properties */
209 gate->reg = reg;
210 gate->bit_idx = data->enable;
211 gate->lock = factors->lock;
212 gate_hw = &gate->hw;
213 }
214
215 /* Add a mux if this factor clock can be muxed */
216 if (data->mux) {
217 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
218 if (!mux) {
219 kfree(factors);
220 kfree(gate);
221 return NULL;
222 }
223
224 /* set up gate properties */
225 mux->reg = reg;
226 mux->shift = data->mux;
227 mux->mask = data->muxmask;
228 mux->lock = factors->lock;
229 mux_hw = &mux->hw;
230 }
231
232 clk = clk_register_composite(NULL, clk_name,
233 parents, i,
234 mux_hw, &clk_mux_ops,
235 &factors->hw, &clk_factors_ops,
236 gate_hw, &clk_gate_ops, 0);
237
238 if (!IS_ERR(clk)) {
239 of_clk_add_provider(node, of_clk_src_simple_get, clk);
240 clk_register_clkdev(clk, clk_name, NULL);
241 }
242
243 return clk;
244 }
245