1 #ifndef __iop_fifo_out_defs_h 2 #define __iop_fifo_out_defs_h 3 4 /* 5 * This file is autogenerated from 6 * file: ../../inst/io_proc/rtl/iop_fifo_out.r 7 * id: <not found> 8 * last modfied: Mon Apr 11 16:10:09 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r 11 * id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 /* Main access macros */ 17 #ifndef REG_RD 18 #define REG_RD( scope, inst, reg ) \ 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #endif 22 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #endif 28 29 #ifndef REG_RD_VECT 30 #define REG_RD_VECT( scope, inst, reg, index ) \ 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) 34 #endif 35 36 #ifndef REG_WR_VECT 37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ 38 REG_WRITE( reg_##scope##_##reg, \ 39 (inst) + REG_WR_ADDR_##scope##_##reg + \ 40 (index) * STRIDE_##scope##_##reg, (val) ) 41 #endif 42 43 #ifndef REG_RD_INT 44 #define REG_RD_INT( scope, inst, reg ) \ 45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 46 #endif 47 48 #ifndef REG_WR_INT 49 #define REG_WR_INT( scope, inst, reg, val ) \ 50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 51 #endif 52 53 #ifndef REG_RD_INT_VECT 54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ 55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 56 (index) * STRIDE_##scope##_##reg ) 57 #endif 58 59 #ifndef REG_WR_INT_VECT 60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 62 (index) * STRIDE_##scope##_##reg, (val) ) 63 #endif 64 65 #ifndef REG_TYPE_CONV 66 #define REG_TYPE_CONV( type, orgtype, val ) \ 67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 68 #endif 69 70 #ifndef reg_page_size 71 #define reg_page_size 8192 72 #endif 73 74 #ifndef REG_ADDR 75 #define REG_ADDR( scope, inst, reg ) \ 76 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 77 #endif 78 79 #ifndef REG_ADDR_VECT 80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 82 (index) * STRIDE_##scope##_##reg ) 83 #endif 84 85 /* C-code for register scope iop_fifo_out */ 86 87 /* Register rw_cfg, scope iop_fifo_out, type rw */ 88 typedef struct { 89 unsigned int free_lim : 3; 90 unsigned int byte_order : 2; 91 unsigned int trig : 2; 92 unsigned int last_dis_dif_in : 1; 93 unsigned int mode : 2; 94 unsigned int delay_out_last : 1; 95 unsigned int last_dis_dif_out : 1; 96 unsigned int dummy1 : 20; 97 } reg_iop_fifo_out_rw_cfg; 98 #define REG_RD_ADDR_iop_fifo_out_rw_cfg 0 99 #define REG_WR_ADDR_iop_fifo_out_rw_cfg 0 100 101 /* Register rw_ctrl, scope iop_fifo_out, type rw */ 102 typedef struct { 103 unsigned int dif_in_en : 1; 104 unsigned int dif_out_en : 1; 105 unsigned int dummy1 : 30; 106 } reg_iop_fifo_out_rw_ctrl; 107 #define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4 108 #define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4 109 110 /* Register r_stat, scope iop_fifo_out, type r */ 111 typedef struct { 112 unsigned int avail_bytes : 4; 113 unsigned int last : 8; 114 unsigned int dif_in_en : 1; 115 unsigned int dif_out_en : 1; 116 unsigned int zero_data_last : 1; 117 unsigned int dummy1 : 17; 118 } reg_iop_fifo_out_r_stat; 119 #define REG_RD_ADDR_iop_fifo_out_r_stat 8 120 121 /* Register rw_wr1byte, scope iop_fifo_out, type rw */ 122 typedef struct { 123 unsigned int data : 8; 124 unsigned int dummy1 : 24; 125 } reg_iop_fifo_out_rw_wr1byte; 126 #define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12 127 #define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12 128 129 /* Register rw_wr2byte, scope iop_fifo_out, type rw */ 130 typedef struct { 131 unsigned int data : 16; 132 unsigned int dummy1 : 16; 133 } reg_iop_fifo_out_rw_wr2byte; 134 #define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16 135 #define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16 136 137 /* Register rw_wr3byte, scope iop_fifo_out, type rw */ 138 typedef struct { 139 unsigned int data : 24; 140 unsigned int dummy1 : 8; 141 } reg_iop_fifo_out_rw_wr3byte; 142 #define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20 143 #define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20 144 145 /* Register rw_wr4byte, scope iop_fifo_out, type rw */ 146 typedef struct { 147 unsigned int data : 32; 148 } reg_iop_fifo_out_rw_wr4byte; 149 #define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24 150 #define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24 151 152 /* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ 153 typedef struct { 154 unsigned int data : 8; 155 unsigned int dummy1 : 24; 156 } reg_iop_fifo_out_rw_wr1byte_last; 157 #define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28 158 #define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28 159 160 /* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ 161 typedef struct { 162 unsigned int data : 16; 163 unsigned int dummy1 : 16; 164 } reg_iop_fifo_out_rw_wr2byte_last; 165 #define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32 166 #define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32 167 168 /* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ 169 typedef struct { 170 unsigned int data : 24; 171 unsigned int dummy1 : 8; 172 } reg_iop_fifo_out_rw_wr3byte_last; 173 #define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36 174 #define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36 175 176 /* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ 177 typedef struct { 178 unsigned int data : 32; 179 } reg_iop_fifo_out_rw_wr4byte_last; 180 #define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40 181 #define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40 182 183 /* Register rw_set_last, scope iop_fifo_out, type rw */ 184 typedef unsigned int reg_iop_fifo_out_rw_set_last; 185 #define REG_RD_ADDR_iop_fifo_out_rw_set_last 44 186 #define REG_WR_ADDR_iop_fifo_out_rw_set_last 44 187 188 /* Register rs_rd_data, scope iop_fifo_out, type rs */ 189 typedef unsigned int reg_iop_fifo_out_rs_rd_data; 190 #define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48 191 192 /* Register r_rd_data, scope iop_fifo_out, type r */ 193 typedef unsigned int reg_iop_fifo_out_r_rd_data; 194 #define REG_RD_ADDR_iop_fifo_out_r_rd_data 52 195 196 /* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ 197 typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out; 198 #define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56 199 #define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56 200 201 /* Register rw_intr_mask, scope iop_fifo_out, type rw */ 202 typedef struct { 203 unsigned int urun : 1; 204 unsigned int last_data : 1; 205 unsigned int dav : 1; 206 unsigned int free : 1; 207 unsigned int orun : 1; 208 unsigned int dummy1 : 27; 209 } reg_iop_fifo_out_rw_intr_mask; 210 #define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60 211 #define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60 212 213 /* Register rw_ack_intr, scope iop_fifo_out, type rw */ 214 typedef struct { 215 unsigned int urun : 1; 216 unsigned int last_data : 1; 217 unsigned int dav : 1; 218 unsigned int free : 1; 219 unsigned int orun : 1; 220 unsigned int dummy1 : 27; 221 } reg_iop_fifo_out_rw_ack_intr; 222 #define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64 223 #define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64 224 225 /* Register r_intr, scope iop_fifo_out, type r */ 226 typedef struct { 227 unsigned int urun : 1; 228 unsigned int last_data : 1; 229 unsigned int dav : 1; 230 unsigned int free : 1; 231 unsigned int orun : 1; 232 unsigned int dummy1 : 27; 233 } reg_iop_fifo_out_r_intr; 234 #define REG_RD_ADDR_iop_fifo_out_r_intr 68 235 236 /* Register r_masked_intr, scope iop_fifo_out, type r */ 237 typedef struct { 238 unsigned int urun : 1; 239 unsigned int last_data : 1; 240 unsigned int dav : 1; 241 unsigned int free : 1; 242 unsigned int orun : 1; 243 unsigned int dummy1 : 27; 244 } reg_iop_fifo_out_r_masked_intr; 245 #define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72 246 247 248 /* Constants */ 249 enum { 250 regk_iop_fifo_out_hi = 0x00000000, 251 regk_iop_fifo_out_neg = 0x00000002, 252 regk_iop_fifo_out_no = 0x00000000, 253 regk_iop_fifo_out_order16 = 0x00000001, 254 regk_iop_fifo_out_order24 = 0x00000002, 255 regk_iop_fifo_out_order32 = 0x00000003, 256 regk_iop_fifo_out_order8 = 0x00000000, 257 regk_iop_fifo_out_pos = 0x00000001, 258 regk_iop_fifo_out_pos_neg = 0x00000003, 259 regk_iop_fifo_out_rw_cfg_default = 0x00000024, 260 regk_iop_fifo_out_rw_ctrl_default = 0x00000000, 261 regk_iop_fifo_out_rw_intr_mask_default = 0x00000000, 262 regk_iop_fifo_out_rw_set_last_default = 0x00000000, 263 regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000, 264 regk_iop_fifo_out_rw_wr1byte_default = 0x00000000, 265 regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000, 266 regk_iop_fifo_out_rw_wr2byte_default = 0x00000000, 267 regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000, 268 regk_iop_fifo_out_rw_wr3byte_default = 0x00000000, 269 regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000, 270 regk_iop_fifo_out_rw_wr4byte_default = 0x00000000, 271 regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000, 272 regk_iop_fifo_out_size16 = 0x00000002, 273 regk_iop_fifo_out_size24 = 0x00000001, 274 regk_iop_fifo_out_size32 = 0x00000000, 275 regk_iop_fifo_out_size8 = 0x00000003, 276 regk_iop_fifo_out_yes = 0x00000001 277 }; 278 #endif /* __iop_fifo_out_defs_h */ 279