1 /* 2 * Copyright (C) 2011-2013 Renesas Electronics Corporation 3 * Copyright (C) 2013 Cogent Embedded, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. 8 */ 9 10 #ifndef __DMA_RCAR_HPBDMA_H 11 #define __DMA_RCAR_HPBDMA_H 12 13 #include <linux/bitops.h> 14 #include <linux/types.h> 15 16 /* Transmit sizes and respective register values */ 17 enum { 18 XMIT_SZ_8BIT = 0, 19 XMIT_SZ_16BIT = 1, 20 XMIT_SZ_32BIT = 2, 21 XMIT_SZ_MAX 22 }; 23 24 /* DMA control register (DCR) bits */ 25 #define HPB_DMAE_DCR_DTAMD (1u << 26) 26 #define HPB_DMAE_DCR_DTAC (1u << 25) 27 #define HPB_DMAE_DCR_DTAU (1u << 24) 28 #define HPB_DMAE_DCR_DTAU1 (1u << 23) 29 #define HPB_DMAE_DCR_SWMD (1u << 22) 30 #define HPB_DMAE_DCR_BTMD (1u << 21) 31 #define HPB_DMAE_DCR_PKMD (1u << 20) 32 #define HPB_DMAE_DCR_CT (1u << 18) 33 #define HPB_DMAE_DCR_ACMD (1u << 17) 34 #define HPB_DMAE_DCR_DIP (1u << 16) 35 #define HPB_DMAE_DCR_SMDL (1u << 13) 36 #define HPB_DMAE_DCR_SPDAM (1u << 12) 37 #define HPB_DMAE_DCR_SDRMD_MASK (3u << 10) 38 #define HPB_DMAE_DCR_SDRMD_MOD (0u << 10) 39 #define HPB_DMAE_DCR_SDRMD_AUTO (1u << 10) 40 #define HPB_DMAE_DCR_SDRMD_TIMER (2u << 10) 41 #define HPB_DMAE_DCR_SPDS_MASK (3u << 8) 42 #define HPB_DMAE_DCR_SPDS_8BIT (0u << 8) 43 #define HPB_DMAE_DCR_SPDS_16BIT (1u << 8) 44 #define HPB_DMAE_DCR_SPDS_32BIT (2u << 8) 45 #define HPB_DMAE_DCR_DMDL (1u << 5) 46 #define HPB_DMAE_DCR_DPDAM (1u << 4) 47 #define HPB_DMAE_DCR_DDRMD_MASK (3u << 2) 48 #define HPB_DMAE_DCR_DDRMD_MOD (0u << 2) 49 #define HPB_DMAE_DCR_DDRMD_AUTO (1u << 2) 50 #define HPB_DMAE_DCR_DDRMD_TIMER (2u << 2) 51 #define HPB_DMAE_DCR_DPDS_MASK (3u << 0) 52 #define HPB_DMAE_DCR_DPDS_8BIT (0u << 0) 53 #define HPB_DMAE_DCR_DPDS_16BIT (1u << 0) 54 #define HPB_DMAE_DCR_DPDS_32BIT (2u << 0) 55 56 /* Asynchronous reset register (ASYNCRSTR) bits */ 57 #define HPB_DMAE_ASYNCRSTR_ASRST41 BIT(10) 58 #define HPB_DMAE_ASYNCRSTR_ASRST40 BIT(9) 59 #define HPB_DMAE_ASYNCRSTR_ASRST39 BIT(8) 60 #define HPB_DMAE_ASYNCRSTR_ASRST27 BIT(7) 61 #define HPB_DMAE_ASYNCRSTR_ASRST26 BIT(6) 62 #define HPB_DMAE_ASYNCRSTR_ASRST25 BIT(5) 63 #define HPB_DMAE_ASYNCRSTR_ASRST24 BIT(4) 64 #define HPB_DMAE_ASYNCRSTR_ASRST23 BIT(3) 65 #define HPB_DMAE_ASYNCRSTR_ASRST22 BIT(2) 66 #define HPB_DMAE_ASYNCRSTR_ASRST21 BIT(1) 67 #define HPB_DMAE_ASYNCRSTR_ASRST20 BIT(0) 68 69 struct hpb_dmae_slave_config { 70 unsigned int id; 71 dma_addr_t addr; 72 u32 dcr; 73 u32 port; 74 u32 rstr; 75 u32 mdr; 76 u32 mdm; 77 u32 flags; 78 #define HPB_DMAE_SET_ASYNC_RESET BIT(0) 79 #define HPB_DMAE_SET_ASYNC_MODE BIT(1) 80 u32 dma_ch; 81 }; 82 83 #define HPB_DMAE_CHANNEL(_irq, _s_id) \ 84 { \ 85 .ch_irq = _irq, \ 86 .s_id = _s_id, \ 87 } 88 89 struct hpb_dmae_channel { 90 unsigned int ch_irq; 91 unsigned int s_id; 92 }; 93 94 struct hpb_dmae_pdata { 95 const struct hpb_dmae_slave_config *slaves; 96 int num_slaves; 97 const struct hpb_dmae_channel *channels; 98 int num_channels; 99 const unsigned int ts_shift[XMIT_SZ_MAX]; 100 int num_hw_channels; 101 }; 102 103 #endif 104