Searched refs:AVIVO_D1GRPH_UPDATE (Results 1 – 4 of 4) sorted by relevance
116 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()121 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()131 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()139 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()147 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
364 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_stop()367 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); in rv515_mc_stop()414 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_resume()417 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); in rv515_mc_resume()425 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_resume()
807 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rv770_page_flip()812 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()829 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rv770_page_flip()837 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()845 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rv770_page_flip_pending()
419 #define AVIVO_D1GRPH_UPDATE 0x6144 macro