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Searched refs:BIT1 (Results 1 – 47 of 47) sorted by relevance

/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8821ae/
Dpwrseq.h51 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
79 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
88 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
91 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
192 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
195 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
275 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
281 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
310 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
316 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
[all …]
/linux-4.1.27/drivers/staging/rtl8188eu/include/
Dpwrseq.h68 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1}, \
71 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0|BIT1, 0}, \
108 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, \
111 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, \
143 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, \
156 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, \
190 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, \
203 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, \
262 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\
292 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, \
[all …]
Drtl8188e_spec.h27 #define BIT1 0x00000002 macro
541 #define CMD_READ_EFUSE_MAP BIT1
552 #define RRSR_2M BIT1
575 #define HAL92C_WOL_GTK_UPDATE_EVENT BIT1
579 #define BW_OPMODE_5G BIT1
611 #define WOW_WOMEN BIT1 /* WoW function on or off. */
641 #define IMR_RDU_88E BIT1 /* Rx Descriptor Unavailable */
704 #define StopVI BIT1
731 #define RCR_APM BIT1 /* Accept physical match pkt */
1201 #define SDIO_HIMR_AVAL_MSK BIT1
[all …]
Drtw_sreset.h34 #define USB_READ_PORT_FAIL BIT1
Dodm.h418 ODM_BB_RA_MASK = BIT1,
464 ODM_RF_TX_B = BIT1,
502 ODM_LINK = BIT1,
516 ODM_WM_G = BIT1,
527 ODM_BAND_5G = BIT1,
Dodm_debug.h61 #define ODM_COMP_RA_MASK BIT1
DHal8188EPhyCfg.h92 WIRELESS_MODE_G = BIT1,
Dosdep_service.h89 #define BIT1 0x00000002 macro
Dhal_intf.h29 RTW_USB = BIT1,
/linux-4.1.27/drivers/scsi/
Ddc395x.h74 #define BIT1 0x00000002 macro
79 #define UNIT_INFO_CHANGED BIT1
85 #define SCSI_SUPPORT BIT1
121 #define RESET_DETECT BIT1
129 #define ABORTION BIT1
141 #define ABORT_DEV BIT1
174 #define SYNC_NEGO_DONE BIT1
630 #define GREATER_1G BIT1
/linux-4.1.27/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h144 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
162 #define RCR_APM BIT1
216 #define SCR_RxUseDK BIT1
241 #define IMR_VODOK BIT1
246 #define TPPoll_BEQ BIT1
286 #define AcmHw_BeqEn BIT1
294 #define AcmFw_ViqStatus BIT1
347 #define BW_OPMODE_5G BIT1
376 #define RRSR_2M BIT1
Drtl_dm.c2266 eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff; in dm_CheckRfCtrlGPIO()
/linux-4.1.27/drivers/video/fbdev/via/
Ddvi.c59 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
66 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
339 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); in dvi_patch_skew_dvp0()
349 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
352 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
359 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
360 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); in dvi_patch_skew_dvp0()
377 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
384 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
391 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
Dlcd.c359 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
534 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
577 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
622 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1); in integrated_lvds_disable()
666 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
668 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
688 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1); in integrated_lvds_enable()
760 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
Dvia_utility.c184 viafb_write_reg_mask(CR6A, VIACR, 0x02, BIT1); in viafb_set_gamma_table()
Dshare.h29 #define BIT1 0x02 macro
Dhw.c964 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); in load_fix_bit_crtc_reg()
975 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1); in load_fix_bit_crtc_reg()
2078 p_gfx_dpa_setting->DVP0DataDri_S, BIT1); in viafb_set_dpa_gfx()
Dviafbdev.c1128 (viafb_read_reg(VIASR, SR1B) & BIT1) >> 1; in viafb_dvp0_proc_show()
1171 reg_val << 1, BIT1); in viafb_dvp0_proc_write()
/linux-4.1.27/drivers/staging/rtl8192u/
Dr8192U_hw.h159 #define RCR_APM BIT1 // Accept physical match packet
184 #define SCR_RxUseDK BIT1 //Force Rx Use Default Key
230 #define AcmHw_BeqEn BIT1
285 #define BW_OPMODE_5G BIT1
308 #define RRSR_2M BIT1
Dr8192U.h47 #define BIT1 0x00000002 macro
91 #define COMP_DBG BIT1
/linux-4.1.27/drivers/staging/rtl8192e/
Drtl819x_Qos.h23 #define BIT1 0x00000002 macro
237 #define GET_VI_UAPSD(_apsd) ((_apsd) & BIT1)
238 #define SET_VI_UAPSD(_apsd) ((_apsd) |= BIT1)
Drtllib.h126 #define RT_RF_OFF_LEVL_CLK_REQ BIT1
/linux-4.1.27/drivers/net/wireless/rtlwifi/btcoexist/
Dhalbt_precomp.h49 #define BIT1 0x00000002 macro
Dhalbtc8821a2ant.h36 #define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1
Dhalbtc8723b2ant.h39 #define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
Dhalbtcoutsrc.h102 #define ALGO_WIFI_RSSI_STATE BIT1
114 #define WIFI_AP_CONNECTED BIT1
Dhalbtc8723b1ant.h36 #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
Dhalbtc8192e2ant.h36 #define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1
Dhalbtc8821a1ant.h38 #define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT1
Dhalbtc8821a2ant.c589 h2c_parameter[0] |= BIT1; in halbtc8821a2ant_set_fw_dec_bt_pwr()
3725 if ((coex_sta->bt_info_ext & BIT1)) { in ex_halbtc8821a2ant_bt_info_notify()
Dhalbtc8723b2ant.c672 h2c_parameter[0] |= BIT1; in btc8723b2ant_set_fw_dec_bt_pwr()
3551 if ((coex_sta->bt_info_ext & BIT1)) { in ex_btc8723b2ant_bt_info_notify()
Dhalbtc8821a1ant.c2769 if (coex_sta->bt_info_ext & BIT1) { in ex_halbtc8821a1ant_bt_info_notify()
Dhalbtc8723b1ant.c2961 if (coex_sta->bt_info_ext & BIT1) { in ex_halbtc8723b1ant_bt_info_notify()
Dhalbtc8192e2ant.c3679 if ((coex_sta->bt_info_ext & BIT1)) { in ex_halbtc8192e2ant_bt_info_notify()
/linux-4.1.27/drivers/staging/rtl8192u/ieee80211/
Drtl819x_Qos.h5 #define BIT1 0x00000002 macro
381 #define GET_VI_UAPSD(_apsd) ((_apsd) & BIT1)
382 #define SET_VI_UAPSD(_apsd) ((_apsd) |= BIT1)
/linux-4.1.27/drivers/staging/rtl8188eu/core/
Drtw_efuse.c409 if (!(word_en&BIT1)) { in Efuse_WordEnableDataWrite()
417 badworden &= (~BIT1); in Efuse_WordEnableDataWrite()
744 if (((pTargetPkt->word_en & BIT1) == 0) && in wordEnMatched()
745 ((pCurPkt->word_en & BIT1) == 0)) in wordEnMatched()
746 match_word_en &= ~BIT1; /* enable word 1 */ in wordEnMatched()
/linux-4.1.27/drivers/tty/
Dsynclink_gt.c221 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
382 #define MASK_PARITY BIT1
1882 if ((status = *(p+1) & (BIT1 + BIT0))) { in rx_async()
1883 if (status & BIT1) in rx_async()
1890 if (status & BIT1) in rx_async()
2068 if (status & BIT1) { in dcd_change()
3907 wr_reg32(info, RDCSR, BIT1); in rdma_reset()
3920 wr_reg32(info, TDCSR, BIT1); in tdma_reset()
3984 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_stop()
4009 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_start()
[all …]
Dsynclink.c495 #define IO_PIN BIT1
514 #define RXSTATUS_OVERRUN BIT1
552 #define TXSTATUS_UNDERRUN BIT1
572 #define MISCSTATUS_BRG1_ZERO BIT1
598 #define SICR_BRG1_ZERO BIT1
632 #define TXSTATUS_UNDERRUN BIT1
637 #define DICR_RECEIVE BIT1
1598 usc_OutDmaReg( info, CDIR, BIT9 | BIT1 ); in mgsl_isr_receive_dma()
5249 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_loopback()
5312 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_aux_clock()
[all …]
Dsynclinkmp.c417 #define TXRDYE BIT1
427 #define BRKD BIT1
428 #define ABTD BIT1
429 #define GAPD BIT1
2587 if (status & BIT1 << shift) in synclinkmp_interrupt()
2596 if (dmastatus & BIT1 << shift) in synclinkmp_interrupt()
4035 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); in enable_loopback()
4053 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); in enable_loopback()
4308 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) { in tx_load_fifo()
4402 RegValue |= BIT1; in async_mode()
[all …]
/linux-4.1.27/drivers/staging/rtl8188eu/hal/
Drtl8188e_hal_init.c211 usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) | BIT1); in hal_notch_filter_8188e()
214 usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1); in hal_notch_filter_8188e()
519 …padapter->pwrctrlpriv.bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT1) ? true… in Hal_ReadPowerSavingMode88E()
Dodm_RTL8188E.c173 phy_set_bb_reg(adapter, 0x864, BIT2|BIT1|BIT0, (AntCombination-1)); in dm_fast_training_init()
235 dm_fat_tbl->antsel_b[mac_id] = (target_ant&BIT1)>>1; in update_tx_ant_88eu()
Dbb_cfg.c716 usb_write16(adapt, REG_SYS_FUNC_EN, (u16)(regval|BIT13|BIT0|BIT1)); in rtl88eu_phy_bb_config()
Dusb_halinit.c610 usb_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1)); in _BeaconFunctionEnable()
811 usb_write8(Adapter, REG_TX_RPT_CTRL, (value8|BIT1|BIT0)); in rtl8188eu_hal_init()
924 usb_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT1)); in CardDisableRTL8188EU()
/linux-4.1.27/include/uapi/linux/
Dsynclink.h19 #define BIT1 0x0002 macro
/linux-4.1.27/drivers/char/pcmcia/
Dsynclink_cs.c302 #define IRQ_OVERRUN BIT1 // receive frame overflow
309 #define CTS BIT1 // CTS state
312 #define PVR_DSR BIT1
683 #define CMD_TXEOM BIT1 // transmit end message
1185 if (gis & (BIT1 | BIT0)) { in mgslpc_isr()
1237 if (pis & BIT1) in mgslpc_isr()
3032 val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0); in loopback_enable()
3167 val |= BIT1; in hdlc_mode()
3186 val |= BIT2 | BIT1; in hdlc_mode()
3612 if (read_reg(info, CHB + STAR) & BIT1) in get_signals()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192de/
Dreg.h385 #define RRSR_2M BIT1
520 #define WOW_WOMEN BIT1 /* WoW function on or off. */
/linux-4.1.27/drivers/scsi/lpfc/
Dlpfc_hw4.h675 #define LPFC_SLI4_INTR1 BIT1