Searched refs:BIT24 (Results 1 – 20 of 20) sorted by relevance
111 #define BIT24 0x01000000 macro301 #define EPn_MODE (BIT25+BIT24)303 #define EPn_INTERRUPT BIT24332 #define EPn_ISO_CRC BIT24 /* R */
72 #define BIT24 0x01000000 macro
1001 u32tmp &= ~BIT24; in halbtc8723b1ant_SetAntPath()1012 u32tmp |= BIT24; in halbtc8723b1ant_SetAntPath()1091 u32tmp &= ~BIT24; in halbtc8723b1ant_SetAntPath()
960 u4_tmp |= BIT24; in halbtc8821a1ant_set_ant_path()995 u4_tmp &= ~BIT24; in halbtc8821a1ant_set_ant_path()
1137 u4tmp |= BIT24; in halbtc8821a2ant_set_ant_path()
1196 u32tmp |= BIT24; in btc8723b2ant_set_ant_path()
50 #define BIT24 0x01000000 macro625 #define IMR_TSF_BIT32_TOGGLE_88E BIT24 /* TSF Timer BIT32 toggle indication interrupt */648 #define IMR_BCNDMAINT4_88E BIT24 /* Beacon DMA Interrupt 4 */714 #define RCR_ENMBID BIT24 /* Enable Multiple BssId. */1216 #define SDIO_HIMR_OCPINT_MSK BIT241242 #define SDIO_HISR_OCPINT BIT24
78 #define ODM_COMP_TX_PWR_TRACK BIT24
112 #define BIT24 0x01000000 macro
436 ODM_RF_TX_PWR_TRACK = BIT24,
129 #define TCR_SAT BIT24 // Enable Rate depedent ack timeout timer147 #define RCR_ACKTXBW (BIT24|BIT25) // TXBW Setting of ACK frames
70 #define BIT24 0x01000000 macro121 #define COMP_FIRMWARE BIT24 /* Firmware downloading */
42 #define BIT24 0x01000000 macro
51 #define BIT24 0x01000000 macro
46 #define BIT24 0x01000000 macro
150 #define RCR_ACKTXBW (BIT24|BIT25)
28 #define BIT24 0x01000000 macro
152 phy_set_bb_reg(adapter, 0x878, BIT25|BIT24|BIT23, 5); in dm_fast_training_init()
1121 phy_set_bb_reg(adapt, rFPGA0_RFMOD, BIT24, 0x00); in phy_iq_calibrate()
698 #define LPFC_SLI4_INTR24 BIT24