1 /*
2 * comedi/drivers/me_daq.c
3 * Hardware driver for Meilhaus data acquisition cards:
4 * ME-2000i, ME-2600i, ME-3000vm1
5 *
6 * Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 /*
20 * Driver: me_daq
21 * Description: Meilhaus PCI data acquisition cards
22 * Devices: [Meilhaus] ME-2600i (me-2600i), ME-2000i (me-2000i)
23 * Author: Michael Hillmann <hillmann@syscongroup.de>
24 * Status: experimental
25 *
26 * Configuration options: not applicable, uses PCI auto config
27 *
28 * Supports:
29 * Analog Input, Analog Output, Digital I/O
30 */
31
32 #include <linux/module.h>
33 #include <linux/interrupt.h>
34 #include <linux/sched.h>
35
36 #include "../comedi_pci.h"
37
38 #include "plx9052.h"
39
40 #define ME2600_FIRMWARE "me2600_firmware.bin"
41
42 #define XILINX_DOWNLOAD_RESET 0x42 /* Xilinx registers */
43
44 #define ME_CONTROL_1 0x0000 /* - | W */
45 #define INTERRUPT_ENABLE (1<<15)
46 #define COUNTER_B_IRQ (1<<12)
47 #define COUNTER_A_IRQ (1<<11)
48 #define CHANLIST_READY_IRQ (1<<10)
49 #define EXT_IRQ (1<<9)
50 #define ADFIFO_HALFFULL_IRQ (1<<8)
51 #define SCAN_COUNT_ENABLE (1<<5)
52 #define SIMULTANEOUS_ENABLE (1<<4)
53 #define TRIGGER_FALLING_EDGE (1<<3)
54 #define CONTINUOUS_MODE (1<<2)
55 #define DISABLE_ADC (0<<0)
56 #define SOFTWARE_TRIGGERED_ADC (1<<0)
57 #define SCAN_TRIGGERED_ADC (2<<0)
58 #define EXT_TRIGGERED_ADC (3<<0)
59 #define ME_ADC_START 0x0000 /* R | - */
60 #define ME_CONTROL_2 0x0002 /* - | W */
61 #define ENABLE_ADFIFO (1<<10)
62 #define ENABLE_CHANLIST (1<<9)
63 #define ENABLE_PORT_B (1<<7)
64 #define ENABLE_PORT_A (1<<6)
65 #define ENABLE_COUNTER_B (1<<4)
66 #define ENABLE_COUNTER_A (1<<3)
67 #define ENABLE_DAC (1<<1)
68 #define BUFFERED_DAC (1<<0)
69 #define ME_DAC_UPDATE 0x0002 /* R | - */
70 #define ME_STATUS 0x0004 /* R | - */
71 #define COUNTER_B_IRQ_PENDING (1<<12)
72 #define COUNTER_A_IRQ_PENDING (1<<11)
73 #define CHANLIST_READY_IRQ_PENDING (1<<10)
74 #define EXT_IRQ_PENDING (1<<9)
75 #define ADFIFO_HALFFULL_IRQ_PENDING (1<<8)
76 #define ADFIFO_FULL (1<<4)
77 #define ADFIFO_HALFFULL (1<<3)
78 #define ADFIFO_EMPTY (1<<2)
79 #define CHANLIST_FULL (1<<1)
80 #define FST_ACTIVE (1<<0)
81 #define ME_RESET_INTERRUPT 0x0004 /* - | W */
82 #define ME_DIO_PORT_A 0x0006 /* R | W */
83 #define ME_DIO_PORT_B 0x0008 /* R | W */
84 #define ME_TIMER_DATA_0 0x000A /* - | W */
85 #define ME_TIMER_DATA_1 0x000C /* - | W */
86 #define ME_TIMER_DATA_2 0x000E /* - | W */
87 #define ME_CHANNEL_LIST 0x0010 /* - | W */
88 #define ADC_UNIPOLAR (1<<6)
89 #define ADC_GAIN_0 (0<<4)
90 #define ADC_GAIN_1 (1<<4)
91 #define ADC_GAIN_2 (2<<4)
92 #define ADC_GAIN_3 (3<<4)
93 #define ME_READ_AD_FIFO 0x0010 /* R | - */
94 #define ME_DAC_CONTROL 0x0012 /* - | W */
95 #define DAC_UNIPOLAR_D (0<<4)
96 #define DAC_BIPOLAR_D (1<<4)
97 #define DAC_UNIPOLAR_C (0<<5)
98 #define DAC_BIPOLAR_C (1<<5)
99 #define DAC_UNIPOLAR_B (0<<6)
100 #define DAC_BIPOLAR_B (1<<6)
101 #define DAC_UNIPOLAR_A (0<<7)
102 #define DAC_BIPOLAR_A (1<<7)
103 #define DAC_GAIN_0_D (0<<8)
104 #define DAC_GAIN_1_D (1<<8)
105 #define DAC_GAIN_0_C (0<<9)
106 #define DAC_GAIN_1_C (1<<9)
107 #define DAC_GAIN_0_B (0<<10)
108 #define DAC_GAIN_1_B (1<<10)
109 #define DAC_GAIN_0_A (0<<11)
110 #define DAC_GAIN_1_A (1<<11)
111 #define ME_DAC_CONTROL_UPDATE 0x0012 /* R | - */
112 #define ME_DAC_DATA_A 0x0014 /* - | W */
113 #define ME_DAC_DATA_B 0x0016 /* - | W */
114 #define ME_DAC_DATA_C 0x0018 /* - | W */
115 #define ME_DAC_DATA_D 0x001A /* - | W */
116 #define ME_COUNTER_ENDDATA_A 0x001C /* - | W */
117 #define ME_COUNTER_ENDDATA_B 0x001E /* - | W */
118 #define ME_COUNTER_STARTDATA_A 0x0020 /* - | W */
119 #define ME_COUNTER_VALUE_A 0x0020 /* R | - */
120 #define ME_COUNTER_STARTDATA_B 0x0022 /* - | W */
121 #define ME_COUNTER_VALUE_B 0x0022 /* R | - */
122
123 static const struct comedi_lrange me_ai_range = {
124 8, {
125 BIP_RANGE(10),
126 BIP_RANGE(5),
127 BIP_RANGE(2.5),
128 BIP_RANGE(1.25),
129 UNI_RANGE(10),
130 UNI_RANGE(5),
131 UNI_RANGE(2.5),
132 UNI_RANGE(1.25)
133 }
134 };
135
136 static const struct comedi_lrange me_ao_range = {
137 3, {
138 BIP_RANGE(10),
139 BIP_RANGE(5),
140 UNI_RANGE(10)
141 }
142 };
143
144 enum me_boardid {
145 BOARD_ME2600,
146 BOARD_ME2000,
147 };
148
149 struct me_board {
150 const char *name;
151 int needs_firmware;
152 int has_ao;
153 };
154
155 static const struct me_board me_boards[] = {
156 [BOARD_ME2600] = {
157 .name = "me-2600i",
158 .needs_firmware = 1,
159 .has_ao = 1,
160 },
161 [BOARD_ME2000] = {
162 .name = "me-2000i",
163 },
164 };
165
166 struct me_private_data {
167 void __iomem *plx_regbase; /* PLX configuration base address */
168
169 unsigned short control_1; /* Mirror of CONTROL_1 register */
170 unsigned short control_2; /* Mirror of CONTROL_2 register */
171 unsigned short dac_control; /* Mirror of the DAC_CONTROL register */
172 };
173
sleep(unsigned sec)174 static inline void sleep(unsigned sec)
175 {
176 __set_current_state(TASK_INTERRUPTIBLE);
177 schedule_timeout(sec * HZ);
178 }
179
me_dio_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)180 static int me_dio_insn_config(struct comedi_device *dev,
181 struct comedi_subdevice *s,
182 struct comedi_insn *insn,
183 unsigned int *data)
184 {
185 struct me_private_data *devpriv = dev->private;
186 unsigned int chan = CR_CHAN(insn->chanspec);
187 unsigned int mask;
188 int ret;
189
190 if (chan < 16)
191 mask = 0x0000ffff;
192 else
193 mask = 0xffff0000;
194
195 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
196 if (ret)
197 return ret;
198
199 if (s->io_bits & 0x0000ffff)
200 devpriv->control_2 |= ENABLE_PORT_A;
201 else
202 devpriv->control_2 &= ~ENABLE_PORT_A;
203 if (s->io_bits & 0xffff0000)
204 devpriv->control_2 |= ENABLE_PORT_B;
205 else
206 devpriv->control_2 &= ~ENABLE_PORT_B;
207
208 writew(devpriv->control_2, dev->mmio + ME_CONTROL_2);
209
210 return insn->n;
211 }
212
me_dio_insn_bits(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)213 static int me_dio_insn_bits(struct comedi_device *dev,
214 struct comedi_subdevice *s,
215 struct comedi_insn *insn,
216 unsigned int *data)
217 {
218 void __iomem *mmio_porta = dev->mmio + ME_DIO_PORT_A;
219 void __iomem *mmio_portb = dev->mmio + ME_DIO_PORT_B;
220 unsigned int mask;
221 unsigned int val;
222
223 mask = comedi_dio_update_state(s, data);
224 if (mask) {
225 if (mask & 0x0000ffff)
226 writew((s->state & 0xffff), mmio_porta);
227 if (mask & 0xffff0000)
228 writew(((s->state >> 16) & 0xffff), mmio_portb);
229 }
230
231 if (s->io_bits & 0x0000ffff)
232 val = s->state & 0xffff;
233 else
234 val = readw(mmio_porta);
235
236 if (s->io_bits & 0xffff0000)
237 val |= (s->state & 0xffff0000);
238 else
239 val |= (readw(mmio_portb) << 16);
240
241 data[1] = val;
242
243 return insn->n;
244 }
245
me_ai_eoc(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned long context)246 static int me_ai_eoc(struct comedi_device *dev,
247 struct comedi_subdevice *s,
248 struct comedi_insn *insn,
249 unsigned long context)
250 {
251 unsigned int status;
252
253 status = readw(dev->mmio + ME_STATUS);
254 if ((status & 0x0004) == 0)
255 return 0;
256 return -EBUSY;
257 }
258
me_ai_insn_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)259 static int me_ai_insn_read(struct comedi_device *dev,
260 struct comedi_subdevice *s,
261 struct comedi_insn *insn,
262 unsigned int *data)
263 {
264 struct me_private_data *dev_private = dev->private;
265 unsigned int chan = CR_CHAN(insn->chanspec);
266 unsigned int rang = CR_RANGE(insn->chanspec);
267 unsigned int aref = CR_AREF(insn->chanspec);
268 unsigned short val;
269 int ret;
270
271 /* stop any running conversion */
272 dev_private->control_1 &= 0xFFFC;
273 writew(dev_private->control_1, dev->mmio + ME_CONTROL_1);
274
275 /* clear chanlist and ad fifo */
276 dev_private->control_2 &= ~(ENABLE_ADFIFO | ENABLE_CHANLIST);
277 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
278
279 /* reset any pending interrupt */
280 writew(0x00, dev->mmio + ME_RESET_INTERRUPT);
281
282 /* enable the chanlist and ADC fifo */
283 dev_private->control_2 |= (ENABLE_ADFIFO | ENABLE_CHANLIST);
284 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
285
286 /* write to channel list fifo */
287 val = chan & 0x0f; /* b3:b0 channel */
288 val |= (rang & 0x03) << 4; /* b5:b4 gain */
289 val |= (rang & 0x04) << 4; /* b6 polarity */
290 val |= ((aref & AREF_DIFF) ? 0x80 : 0); /* b7 differential */
291 writew(val & 0xff, dev->mmio + ME_CHANNEL_LIST);
292
293 /* set ADC mode to software trigger */
294 dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC;
295 writew(dev_private->control_1, dev->mmio + ME_CONTROL_1);
296
297 /* start conversion by reading from ADC_START */
298 readw(dev->mmio + ME_ADC_START);
299
300 /* wait for ADC fifo not empty flag */
301 ret = comedi_timeout(dev, s, insn, me_ai_eoc, 0);
302 if (ret)
303 return ret;
304
305 /* get value from ADC fifo */
306 val = readw(dev->mmio + ME_READ_AD_FIFO);
307 val = (val ^ 0x800) & 0x0fff;
308 data[0] = val;
309
310 /* stop any running conversion */
311 dev_private->control_1 &= 0xFFFC;
312 writew(dev_private->control_1, dev->mmio + ME_CONTROL_1);
313
314 return 1;
315 }
316
me_ao_insn_write(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)317 static int me_ao_insn_write(struct comedi_device *dev,
318 struct comedi_subdevice *s,
319 struct comedi_insn *insn,
320 unsigned int *data)
321 {
322 struct me_private_data *dev_private = dev->private;
323 unsigned int chan = CR_CHAN(insn->chanspec);
324 unsigned int rang = CR_RANGE(insn->chanspec);
325 unsigned int val = s->readback[chan];
326 int i;
327
328 /* Enable all DAC */
329 dev_private->control_2 |= ENABLE_DAC;
330 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
331
332 /* and set DAC to "buffered" mode */
333 dev_private->control_2 |= BUFFERED_DAC;
334 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
335
336 /* Set dac-control register */
337 for (i = 0; i < insn->n; i++) {
338 /* clear bits for this channel */
339 dev_private->dac_control &= ~(0x0880 >> chan);
340 if (rang == 0)
341 dev_private->dac_control |=
342 ((DAC_BIPOLAR_A | DAC_GAIN_1_A) >> chan);
343 else if (rang == 1)
344 dev_private->dac_control |=
345 ((DAC_BIPOLAR_A | DAC_GAIN_0_A) >> chan);
346 }
347 writew(dev_private->dac_control, dev->mmio + ME_DAC_CONTROL);
348
349 /* Update dac-control register */
350 readw(dev->mmio + ME_DAC_CONTROL_UPDATE);
351
352 /* Set data register */
353 for (i = 0; i < insn->n; i++) {
354 val = data[i];
355
356 writew(val, dev->mmio + ME_DAC_DATA_A + (chan << 1));
357 }
358 s->readback[chan] = val;
359
360 /* Update dac with data registers */
361 readw(dev->mmio + ME_DAC_UPDATE);
362
363 return insn->n;
364 }
365
me2600_xilinx_download(struct comedi_device * dev,const u8 * data,size_t size,unsigned long context)366 static int me2600_xilinx_download(struct comedi_device *dev,
367 const u8 *data, size_t size,
368 unsigned long context)
369 {
370 struct me_private_data *dev_private = dev->private;
371 unsigned int value;
372 unsigned int file_length;
373 unsigned int i;
374
375 /* disable irq's on PLX */
376 writel(0x00, dev_private->plx_regbase + PLX9052_INTCSR);
377
378 /* First, make a dummy read to reset xilinx */
379 value = readw(dev->mmio + XILINX_DOWNLOAD_RESET);
380
381 /* Wait until reset is over */
382 sleep(1);
383
384 /* Write a dummy value to Xilinx */
385 writeb(0x00, dev->mmio + 0x0);
386 sleep(1);
387
388 /*
389 * Format of the firmware
390 * Build longs from the byte-wise coded header
391 * Byte 1-3: length of the array
392 * Byte 4-7: version
393 * Byte 8-11: date
394 * Byte 12-15: reserved
395 */
396 if (size < 16)
397 return -EINVAL;
398
399 file_length = (((unsigned int)data[0] & 0xff) << 24) +
400 (((unsigned int)data[1] & 0xff) << 16) +
401 (((unsigned int)data[2] & 0xff) << 8) +
402 ((unsigned int)data[3] & 0xff);
403
404 /*
405 * Loop for writing firmware byte by byte to xilinx
406 * Firmware data start at offset 16
407 */
408 for (i = 0; i < file_length; i++)
409 writeb((data[16 + i] & 0xff), dev->mmio + 0x0);
410
411 /* Write 5 dummy values to xilinx */
412 for (i = 0; i < 5; i++)
413 writeb(0x00, dev->mmio + 0x0);
414
415 /* Test if there was an error during download -> INTB was thrown */
416 value = readl(dev_private->plx_regbase + PLX9052_INTCSR);
417 if (value & PLX9052_INTCSR_LI2STAT) {
418 /* Disable interrupt */
419 writel(0x00, dev_private->plx_regbase + PLX9052_INTCSR);
420 dev_err(dev->class_dev, "Xilinx download failed\n");
421 return -EIO;
422 }
423
424 /* Wait until the Xilinx is ready for real work */
425 sleep(1);
426
427 /* Enable PLX-Interrupts */
428 writel(PLX9052_INTCSR_LI1ENAB |
429 PLX9052_INTCSR_LI1POL |
430 PLX9052_INTCSR_PCIENAB,
431 dev_private->plx_regbase + PLX9052_INTCSR);
432
433 return 0;
434 }
435
me_reset(struct comedi_device * dev)436 static int me_reset(struct comedi_device *dev)
437 {
438 struct me_private_data *dev_private = dev->private;
439
440 /* Reset board */
441 writew(0x00, dev->mmio + ME_CONTROL_1);
442 writew(0x00, dev->mmio + ME_CONTROL_2);
443 writew(0x00, dev->mmio + ME_RESET_INTERRUPT);
444 writew(0x00, dev->mmio + ME_DAC_CONTROL);
445
446 /* Save values in the board context */
447 dev_private->dac_control = 0;
448 dev_private->control_1 = 0;
449 dev_private->control_2 = 0;
450
451 return 0;
452 }
453
me_auto_attach(struct comedi_device * dev,unsigned long context)454 static int me_auto_attach(struct comedi_device *dev,
455 unsigned long context)
456 {
457 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
458 const struct me_board *board = NULL;
459 struct me_private_data *dev_private;
460 struct comedi_subdevice *s;
461 int ret;
462
463 if (context < ARRAY_SIZE(me_boards))
464 board = &me_boards[context];
465 if (!board)
466 return -ENODEV;
467 dev->board_ptr = board;
468 dev->board_name = board->name;
469
470 dev_private = comedi_alloc_devpriv(dev, sizeof(*dev_private));
471 if (!dev_private)
472 return -ENOMEM;
473
474 ret = comedi_pci_enable(dev);
475 if (ret)
476 return ret;
477
478 dev_private->plx_regbase = pci_ioremap_bar(pcidev, 0);
479 if (!dev_private->plx_regbase)
480 return -ENOMEM;
481
482 dev->mmio = pci_ioremap_bar(pcidev, 2);
483 if (!dev->mmio)
484 return -ENOMEM;
485
486 /* Download firmware and reset card */
487 if (board->needs_firmware) {
488 ret = comedi_load_firmware(dev, &comedi_to_pci_dev(dev)->dev,
489 ME2600_FIRMWARE,
490 me2600_xilinx_download, 0);
491 if (ret < 0)
492 return ret;
493 }
494 me_reset(dev);
495
496 ret = comedi_alloc_subdevices(dev, 3);
497 if (ret)
498 return ret;
499
500 s = &dev->subdevices[0];
501 s->type = COMEDI_SUBD_AI;
502 s->subdev_flags = SDF_READABLE | SDF_COMMON;
503 s->n_chan = 16;
504 s->maxdata = 0x0fff;
505 s->len_chanlist = 16;
506 s->range_table = &me_ai_range;
507 s->insn_read = me_ai_insn_read;
508
509 s = &dev->subdevices[1];
510 if (board->has_ao) {
511 s->type = COMEDI_SUBD_AO;
512 s->subdev_flags = SDF_WRITABLE | SDF_COMMON;
513 s->n_chan = 4;
514 s->maxdata = 0x0fff;
515 s->len_chanlist = 4;
516 s->range_table = &me_ao_range;
517 s->insn_write = me_ao_insn_write;
518
519 ret = comedi_alloc_subdev_readback(s);
520 if (ret)
521 return ret;
522 } else {
523 s->type = COMEDI_SUBD_UNUSED;
524 }
525
526 s = &dev->subdevices[2];
527 s->type = COMEDI_SUBD_DIO;
528 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
529 s->n_chan = 32;
530 s->maxdata = 1;
531 s->len_chanlist = 32;
532 s->range_table = &range_digital;
533 s->insn_bits = me_dio_insn_bits;
534 s->insn_config = me_dio_insn_config;
535
536 return 0;
537 }
538
me_detach(struct comedi_device * dev)539 static void me_detach(struct comedi_device *dev)
540 {
541 struct me_private_data *dev_private = dev->private;
542
543 if (dev_private) {
544 if (dev->mmio)
545 me_reset(dev);
546 if (dev_private->plx_regbase)
547 iounmap(dev_private->plx_regbase);
548 }
549 comedi_pci_detach(dev);
550 }
551
552 static struct comedi_driver me_daq_driver = {
553 .driver_name = "me_daq",
554 .module = THIS_MODULE,
555 .auto_attach = me_auto_attach,
556 .detach = me_detach,
557 };
558
me_daq_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)559 static int me_daq_pci_probe(struct pci_dev *dev,
560 const struct pci_device_id *id)
561 {
562 return comedi_pci_auto_config(dev, &me_daq_driver, id->driver_data);
563 }
564
565 static const struct pci_device_id me_daq_pci_table[] = {
566 { PCI_VDEVICE(MEILHAUS, 0x2600), BOARD_ME2600 },
567 { PCI_VDEVICE(MEILHAUS, 0x2000), BOARD_ME2000 },
568 { 0 }
569 };
570 MODULE_DEVICE_TABLE(pci, me_daq_pci_table);
571
572 static struct pci_driver me_daq_pci_driver = {
573 .name = "me_daq",
574 .id_table = me_daq_pci_table,
575 .probe = me_daq_pci_probe,
576 .remove = comedi_pci_auto_unconfig,
577 };
578 module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver);
579
580 MODULE_AUTHOR("Comedi http://www.comedi.org");
581 MODULE_DESCRIPTION("Comedi low-level driver");
582 MODULE_LICENSE("GPL");
583 MODULE_FIRMWARE(ME2600_FIRMWARE);
584