Searched refs:DDR2 (Results 1 – 21 of 21) sorted by relevance
19 hex "DDR2 MRS"23 hex "DDR2 SDRAM timing"29 hex "DDR2 config"33 hex "DDR2 latency"
78 @ DDR2 BaseAddr99 @ prepare DDR2 refresh settings120 @ put DDR2 into self-refresh
248 /* DDR2 SDRAM and Test Chip DDR2 I/O supply */257 /* DDR2 SDRAM VTT termination voltage */
16 * Module contains : i.MX287 + 128MB DDR2 + NAND + 2 x Ethernet PHY + RTC
16 * Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC
150 /* DDR2 */
175 /* DDR2 PLL reference clock */
282 /* DDR2 PLL reference clock */
26 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
5 DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
104 case DDR2: in tile_edac_init_csrows()
294 tristate "PPC4xx IBM DDR2 Memory Controller"298 with the IBM DDR2 memory controller found in various
38 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
50 reg = <0x0 0x20000000 // DDR2 512M at 0
47 - axonram: Axon DDR2 device driver
308 tristate "Axon DDR2 memory device driver"312 It registers one block device per Axon's DDR2 memory bank found
117 DDR2 = 0x4, enumerator
131 mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which
1025 DDR2 = 1, /**< DDR2 */ enumerator
273 By default, 2, i.e. 2^2 == 4 DDR2 controllers.
1316 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller