Searched refs:DMA_CNTL (Results 1 – 9 of 9) sorted by relevance
/linux-4.1.27/drivers/gpu/drm/radeon/ |
D | r600_dma.c | 160 dma_cntl = RREG32(DMA_CNTL); in r600_dma_resume() 162 WREG32(DMA_CNTL, dma_cntl); in r600_dma_resume()
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D | ni_dma.c | 239 dma_cntl = RREG32(DMA_CNTL + reg_offset); in cayman_dma_resume() 241 WREG32(DMA_CNTL + reg_offset, dma_cntl); in cayman_dma_resume()
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D | si.c | 5941 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state() 5942 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_disable_interrupt_state() 5943 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state() 5944 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_disable_interrupt_state() 6096 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set() 6097 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set() 6183 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); in si_irq_set() 6184 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); in si_irq_set()
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D | nid.h | 1315 #define DMA_CNTL 0xd02c macro
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D | r600.c | 3530 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_disable_interrupt_state() 3531 WREG32(DMA_CNTL, tmp); in r600_disable_interrupt_state() 3712 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_irq_set() 3781 WREG32(DMA_CNTL, dma_cntl); in r600_irq_set()
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D | sid.h | 1831 #define DMA_CNTL 0xd02c macro
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D | evergreen.c | 4506 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state() 4507 WREG32(DMA_CNTL, tmp); in evergreen_disable_interrupt_state() 4595 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_irq_set() 4723 WREG32(DMA_CNTL, dma_cntl); in evergreen_irq_set()
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D | evergreend.h | 1404 #define DMA_CNTL 0xd02c macro
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D | r600d.h | 631 #define DMA_CNTL 0xd02c macro
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