Searched refs:DSCR (Results 1 – 7 of 7) sorted by relevance
| /linux-4.1.27/Documentation/ABI/stable/ |
| D | sysfs-devices-system-cpu | 16 Description: Default value for the Data Stream Control Register (DSCR) on
19 for any process that has not set the DSCR itself.
20 If a process ever sets the DSCR (via direct access to the
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| /linux-4.1.27/Documentation/devicetree/bindings/c6x/ |
| D | dscr.txt | 8 In general, the Device State Configuration Registers (DSCR) will provide one or
15 the DSCR block may provide registers which are used to reset peripherals,
51 registers in DSCR. On SoCs using kick registers, the first key must be
81 for device states controlled by the DSCR. Each tuple describes a range of
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| D | timer64.txt | 15 - ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface.
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| D | emifa.txt | 18 - ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR
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| /linux-4.1.27/drivers/dma/ |
| D | at_hdmac.c | 237 channel_readl(atchan, DSCR)); in atc_dostart()
249 channel_writel(atchan, DSCR, first->txd.phys); in atc_dostart()
349 dscr = channel_readl(atchan, DSCR); in atc_get_bytes_left()
536 channel_readl(atchan, DSCR)); in atc_handle_cyclic()
1857 atchan->save_dscr = channel_readl(atchan, DSCR); in atc_suspend_cyclic()
1895 channel_writel(atchan, DSCR, atchan->save_dscr); in atc_resume_cyclic()
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| D | at_hdmac_regs.h | 369 channel_readl(atchan, DSCR)); in vdbg_dump_regs()
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| /linux-4.1.27/drivers/staging/dgap/ |
| D | dgap.h | 463 #define DSCR "32" macro
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