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Searched refs:EVERGREEN_CRTC0_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Devergreen_reg.h224 #define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0) macro
Devergreen.c40 EVERGREEN_CRTC0_REGISTER_OFFSET,
4510 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4521 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4588 …afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4730 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in evergreen_irq_set()
4741 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in evergreen_irq_set()
4769 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1); in evergreen_irq_set()
4792 …ev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); in evergreen_irq_ack()
4803 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); in evergreen_irq_ack()
4811 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
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Dradeon_display.c1497 EVERGREEN_CRTC0_REGISTER_OFFSET, in radeon_afmt_init()
1809 EVERGREEN_CRTC0_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
1811 EVERGREEN_CRTC0_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
Dsi.c5948 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5961 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
6194 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in si_irq_set()
6207 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in si_irq_set()
6255 …ev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); in si_irq_ack()
6267 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6271 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6273 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
Dradeon_dp_mst.c14 static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET, in radeon_atom_set_enc_offset()
Dcik.c7305 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7317 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7588 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in cik_irq_set()
7600 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_set()
7653 EVERGREEN_CRTC0_REGISTER_OFFSET); in cik_irq_ack()
7670 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_ack()
7676 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7678 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
Dradeon_device.c657 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | in radeon_card_posted()
Devergreen_cs.c1025 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC0_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
1033 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
Datombios_crtc.c2216 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; in radeon_atombios_init_crtc()