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Searched refs:EVERGREEN_CRTC1_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Devergreen_reg.h225 #define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0) macro
Devergreen.c41 EVERGREEN_CRTC1_REGISTER_OFFSET,
4511 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4522 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4589 …afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4731 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in evergreen_irq_set()
4743 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in evergreen_irq_set()
4770 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2); in evergreen_irq_set()
4793 …ev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); in evergreen_irq_ack()
4804 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); in evergreen_irq_ack()
4813 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
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Dradeon_display.c1498 EVERGREEN_CRTC1_REGISTER_OFFSET, in radeon_afmt_init()
1816 EVERGREEN_CRTC1_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
1818 EVERGREEN_CRTC1_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
Dsi.c5949 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5962 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
6195 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in si_irq_set()
6209 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in si_irq_set()
6256 …ev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); in si_irq_ack()
6269 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6275 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6277 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
Dradeon_dp_mst.c15 EVERGREEN_CRTC1_REGISTER_OFFSET, in radeon_atom_set_enc_offset()
Dcik.c7306 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7318 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7589 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in cik_irq_set()
7602 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_set()
7655 EVERGREEN_CRTC1_REGISTER_OFFSET); in cik_irq_ack()
7673 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_ack()
7680 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7682 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
Dradeon_device.c658 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); in radeon_card_posted()
Devergreen_cs.c1026 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC1_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
1034 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
Datombios_crtc.c2219 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; in radeon_atombios_init_crtc()