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Searched refs:EVERGREEN_CRTC5_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Devergreen_reg.h229 #define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0) macro
Devergreen.c45 EVERGREEN_CRTC5_REGISTER_OFFSET
4518 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4529 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4593 …afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4738 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in evergreen_irq_set()
4754 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in evergreen_irq_set()
4774 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6); in evergreen_irq_set()
4800 …ev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); in evergreen_irq_ack()
4808 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); in evergreen_irq_ack()
4842 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
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Dradeon_display.c1502 EVERGREEN_CRTC5_REGISTER_OFFSET, in radeon_afmt_init()
1844 EVERGREEN_CRTC5_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
1846 EVERGREEN_CRTC5_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
Dsi.c5957 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5970 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
6203 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in si_irq_set()
6221 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in si_irq_set()
6263 …ev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); in si_irq_ack()
6298 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6304 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6306 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
Dradeon_dp_mst.c19 EVERGREEN_CRTC5_REGISTER_OFFSET, in radeon_atom_set_enc_offset()
Dcik.c7313 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7326 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7596 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in cik_irq_set()
7614 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_set()
7666 EVERGREEN_CRTC5_REGISTER_OFFSET); in cik_irq_ack()
7706 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_ack()
7713 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7715 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
Dradeon_device.c665 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); in radeon_card_posted()
Devergreen_cs.c1030 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC5_REGISTER_OFFSET in evergreen_cs_packet_parse_vline()
1038 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET in evergreen_cs_packet_parse_vline()
Datombios_crtc.c2231 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; in radeon_atombios_init_crtc()