Searched refs:EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG (Results 1 – 2 of 2) sorted by relevance
407 { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },525 { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
425 #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260 macro