Searched refs:IS_G4X (Results 1 – 14 of 14) sorted by relevance
60 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) in i915_save_display()98 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) in i915_restore_display()
559 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { in intel_fbc_update()588 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && in intel_fbc_update()
684 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { in i915_get_crtc_scanoutpos()746 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { in i915_get_crtc_scanoutpos()1625 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) in i9xx_pipe_crc_irq_handler()1758 if (IS_G4X(dev)) { in i9xx_hpd_irq_handler()1768 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && in i9xx_hpd_irq_handler()2418 if (IS_G4X(dev)) { in i915_report_and_clear_eir()3984 if (IS_G4X(dev)) in i965_irq_postinstall()3999 if (IS_G4X(dev)) { in i965_irq_postinstall()4041 if (IS_G4X(dev)) in i915_hpd_irq_setup()4248 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { in intel_irq_init()
439 if (IS_G4X(dev) && !IS_GM45(dev)) in intel_crt_detect_hotplug()752 if (ret || !IS_G4X(dev)) in intel_crt_get_modes()
925 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) in hdmi_portclock_limit()1704 } else if (IS_G4X(dev)) { in intel_hdmi_init_connector()1737 if (IS_G4X(dev) && !IS_GM45(dev)) { in intel_hdmi_init_connector()1798 if (IS_G4X(dev)) in intel_hdmi_init()
78 if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) { in i915_stolen_to_physical()
453 if (IS_G4X(dev)) { in intel_init_audio()
1670 else if (IS_CRESTLINE(dev) || IS_G4X(dev) || in i915_sr_status()3391 if (!IS_G4X(dev)) in i9xx_pipe_crc_ctl_reg()3397 if (!IS_G4X(dev)) in i9xx_pipe_crc_ctl_reg()3403 if (!IS_G4X(dev)) in i9xx_pipe_crc_ctl_reg()3427 WARN_ON(!IS_G4X(dev)); in i9xx_pipe_crc_ctl_reg()3687 if (IS_G4X(dev)) in pipe_crc_set_source()
2295 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) macro2388 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))2389 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
516 else if (IS_G4X(dev)) { in intel_limit()2753 if (IS_G4X(dev)) in i9xx_update_primary_plane()3094 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) in intel_prepare_reset()3125 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { in intel_finish_reset()5857 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && in intel_crtc_compute_config()5861 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { in intel_crtc_compute_config()6512 if (IS_G4X(dev) && reduced_clock) in i9xx_update_pll()6734 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { in i9xx_set_pipeconf()7056 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { in i9xx_get_pipe_config()9592 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) in page_flip_finished()[all …]
1426 else if (IS_G4X(dev)) in intel_gpu_reset()
1194 if (IS_G4X(dev)) { in intel_dp_set_clock()5586 if (IS_G4X(dev) && !IS_GM45(dev)) { in intel_dp_init_connector()
163 (IS_G4X(dev) || IS_GEN5(dev))) in gen4_render_ring_flush()
316 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { in intel_set_memory_cxsr()6600 } else if (IS_G4X(dev)) { in intel_init_pm()