Searched refs:ORION5X_BRIDGE_VIRT_BASE (Results 1 – 3 of 3) sorted by relevance
16 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)18 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)20 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)23 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)25 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)27 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)31 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)33 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)35 #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300)
84 #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000) macro
264 orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, in orion5x_timer_init()