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Searched refs:PIPE_C (Results 1 – 10 of 10) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_runtime_pm.c199 1 << PIPE_C | 1 << PIPE_B); in hsw_power_well_post_enable()
223 1 << PIPE_C | 1 << PIPE_B); in skl_power_well_post_enable()
659 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | in chv_dpio_cmn_power_well_enable()
687 assert_pll_disabled(dev_priv, PIPE_C); in chv_dpio_cmn_power_well_disable()
770 power_well->data != PIPE_C); in chv_pipe_power_well_enable()
797 power_well->data != PIPE_C); in chv_pipe_power_well_disable()
1178 .data = PIPE_C,
Dintel_dp_mst.c431 for (i = PIPE_A; i <= PIPE_C; i++) { in intel_dp_add_mst_connector()
537 for (i = PIPE_A; i <= PIPE_C; i++) in intel_dp_create_fake_mst_encoders()
Dintel_pm.c378 case PIPE_C: in vlv_get_fifo_size()
873 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | in vlv_write_wm_values()
874 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); in vlv_write_wm_values()
876 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | in vlv_write_wm_values()
877 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); in vlv_write_wm_values()
880 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | in vlv_write_wm_values()
881 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | in vlv_write_wm_values()
882 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | in vlv_write_wm_values()
995 if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) { in vlv_compute_sr_wm()
2468 if (dirty & WM_DIRTY_PIPE(PIPE_C)) in ilk_write_wm_values()
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Di915_irq.c1701 case PIPE_C: in valleyview_pipestat_irq_handler()
3117 if (pipe_mask & 1 << PIPE_C) in gen8_irq_power_well_post_enable()
3118 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, in gen8_irq_power_well_post_enable()
3119 dev_priv->de_irq_mask[PIPE_C], in gen8_irq_power_well_post_enable()
3120 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); in gen8_irq_power_well_post_enable()
3460 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; in gen8_de_irq_postinstall()
Dintel_ddi.c1338 case PIPE_C: in intel_ddi_enable_transcoder_func()
1474 *pipe = PIPE_C; in intel_ddi_get_hw_state()
Di915_cmd_parser.c455 GEN7_PIPE_DE_LOAD_SL(PIPE_C),
Dintel_drv.h710 case PIPE_C: in vlv_pipe_to_channel()
Di915_debugfs.c3165 .pipe = PIPE_C,
3355 case PIPE_C: in vlv_pipe_crc_ctl_reg()
3456 case PIPE_C: in vlv_undo_pipe_scramble_reset()
Dintel_display.c3943 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); in cpt_set_fdi_bc_bifurcation()
3968 case PIPE_C: in ivybridge_update_fdi_bc_bifurcation()
5738 pipe_required_fdi_lanes(dev, PIPE_C) > 0) { in ironlake_check_fdi_lanes()
5744 case PIPE_C: in ironlake_check_fdi_lanes()
6646 (pipe == PIPE_B || pipe == PIPE_C)) in intel_set_pipe_timings()
8602 trans_edp_pipe = PIPE_C; in haswell_get_pipe_config()
Di915_drv.h112 PIPE_C, enumerator