| /linux-4.1.27/arch/arm/boot/dts/ |
| D | stih415-clock.dtsi | 60 <&clk_s_a0_pll 2>; /* PLL1 */
75 <&clk_s_a0_pll 2>; /* PLL1 */
118 <&clk_s_a1_pll 2>; /* PLL1 */
133 <&clk_s_a1_pll 2>; /* PLL1 */
194 <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */
213 <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */
232 <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */
251 <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */
308 <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */
327 <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
[all …]
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| D | stih416-clock.dtsi | 61 <&clk_s_a0_pll 2>; /* PLL1 */
76 <&clk_s_a0_pll 2>; /* PLL1 */
119 <&clk_s_a1_pll 2>; /* PLL1 */
134 <&clk_s_a1_pll 2>; /* PLL1 */
196 <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */
215 <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */
234 <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */
253 <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */
310 <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */
329 <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
[all …]
|
| D | ste-nomadik-stn8815.dtsi | 172 * that is parent of TIMCLK, PLL1 and PLL2
194 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
202 /* HCLK divides the PLL1 with 1,2,3 or 4 */
|
| D | sun8i-a23.dtsi | 143 * PLL1 is listed twice here.
|
| D | sun6i-a31.dtsi | 176 * PLL1 is listed twice here.
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| /linux-4.1.27/arch/arm/mach-w90x900/ |
| D | clksel.c | 28 #define PLL1 0x01 macro
80 clkval = PLL1; in nuc900_clock_source()
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| /linux-4.1.27/sound/soc/codecs/ |
| D | ak4642.c | 117 #define PLL1 (1 << 5) macro
119 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
355 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
358 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
375 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
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| /linux-4.1.27/Documentation/arm/sunxi/ |
| D | clocks.txt | 19 PLL1
30 PLL1 |
|
| /linux-4.1.27/arch/avr32/boards/favr-32/ |
| D | Kconfig | 11 will use PLL1 to generate a frequency as close as possible to this
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| /linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/ |
| D | qcom,mmcc-msm8960.h | 134 #define PLL1 117 macro
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| /linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| D | qcom,mmcc-msm8960.h | 134 #define PLL1 117 macro
|
| /linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/ |
| D | qcom,mmcc-msm8960.h | 134 #define PLL1 117 macro
|
| /linux-4.1.27/include/dt-bindings/clock/ |
| D | qcom,mmcc-msm8960.h | 134 #define PLL1 117 macro
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| /linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/ |
| D | qcom,mmcc-msm8960.h | 134 #define PLL1 117 macro
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| /linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| D | qcom,mmcc-msm8960.h | 134 #define PLL1 117 macro
|
| /linux-4.1.27/Documentation/devicetree/bindings/clock/st/ |
| D | st,clkgen-divmux.txt | 37 <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
|
| D | st,flexgen.txt | 31 | | |PLL1 | | | | | | | | | |
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| /linux-4.1.27/arch/avr32/mach-at32ap/ |
| D | at32ap700x.c | 209 ctrl = pm_readl(PLL1); in pll1_mode()
219 pm_writel(PLL1, ctrl); in pll1_mode()
234 pm_writel(PLL1, ctrl); in pll1_mode()
242 control = pm_readl(PLL1); in pll1_get_rate()
261 pm_writel(PLL1, ctrl); in pll1_set_rate()
274 ctrl = pm_readl(PLL1); in pll1_set_parent()
284 pm_writel(PLL1, ctrl); in pll1_set_parent()
2299 if (pm_readl(PLL1) & PM_BIT(PLLOSC)) in setup_platform()
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| D | clock.c | 271 seq_printf(s, "PLL1 = %8x\n", pm_readl(PLL1)); in clk_show()
|
| /linux-4.1.27/Documentation/devicetree/bindings/clock/ |
| D | st,nomadik.txt | 30 - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
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| /linux-4.1.27/drivers/media/dvb-frontends/ |
| D | zl10039.c | 54 PLL1, enumerator
|