Searched refs:RADEON_MCLK_CNTL (Results 1 – 5 of 5) sorted by relevance
83 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; in radeon_legacy_get_memory_clock()600 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()615 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()630 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()807 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()812 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()877 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()880 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
694 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); in radeon_do_engine_reset()696 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | in radeon_do_engine_reset()727 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); in radeon_do_engine_reset()
3154 (RADEON_MCLK_CNTL); in combios_parse_pll_table()3157 WREG32_PLL(RADEON_MCLK_CNTL, in combios_parse_pll_table()
795 #define RADEON_MCLK_CNTL 0x0012 macro
1175 #define RADEON_MCLK_CNTL 0x0012 /* PLL */ macro