Searched refs:RADEON_PCIE_TX_GART_CNTL (Results 1 – 4 of 4) sorted by relevance
64 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()65 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); in rv370_pcie_gart_tlb_flush()66 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()67 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_tlb_flush()137 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable()150 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_enable()153 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable()170 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_disable()172 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); in rv370_pcie_gart_disable()572 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_debugfs_pcie_gart_info()
1057 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); in radeon_set_pciegart()1076 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, in radeon_set_pciegart()1079 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, in radeon_set_pciegart()
537 #define RADEON_PCIE_TX_GART_CNTL 0x10 macro
3683 #define RADEON_PCIE_TX_GART_CNTL 0x10 macro