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Searched refs:RX_DESC_NUM (Results 1 – 5 of 5) sorted by relevance

/linux-4.1.27/drivers/net/ethernet/moxa/
Dmoxart_ether.h63 #define RX_DESC_NUM 64 macro
64 #define RX_DESC_NUM_MASK (RX_DESC_NUM-1)
302 dma_addr_t rx_mapping[RX_DESC_NUM];
305 unsigned char *rx_buf[RX_DESC_NUM];
313 unsigned char *tx_buf[RX_DESC_NUM];
Dmoxart_ether.c68 for (i = 0; i < RX_DESC_NUM; i++) in moxart_mac_free_memory()
77 dma_free_coherent(NULL, RX_REG_DESC_SIZE * RX_DESC_NUM, in moxart_mac_free_memory()
129 for (i = 0; i < RX_DESC_NUM; i++) { in moxart_mac_setup_desc_ring()
484 RX_DESC_NUM, &priv->rx_base, in moxart_mac_probe()
498 priv->rx_buf_base = kmalloc(priv->rx_buf_size * RX_DESC_NUM, in moxart_mac_probe()
515 netif_napi_add(ndev, &priv->napi, moxart_rx_poll, RX_DESC_NUM); in moxart_mac_probe()
/linux-4.1.27/drivers/net/ethernet/hisilicon/
Dhip04_eth.c114 #define RX_DESC_NUM 128 macro
117 #define RX_NEXT(N) (((N) + 1) & (RX_DESC_NUM-1))
172 unsigned char *rx_buf[RX_DESC_NUM];
173 dma_addr_t rx_phys[RX_DESC_NUM];
258 val = RX_DESC_NUM << PPE_CFG_RX_DEPTH_SHIFT; in hip04_config_fifo()
637 for (i = 0; i < RX_DESC_NUM; i++) { in hip04_mac_open()
674 for (i = 0; i < RX_DESC_NUM; i++) { in hip04_mac_stop()
785 for (i = 0; i < RX_DESC_NUM; i++) { in hip04_alloc_ring()
799 for (i = 0; i < RX_DESC_NUM; i++) in hip04_free_ring()
844 priv->chan = arg.args[1] * RX_DESC_NUM; in hip04_mac_probe()
Dhix5hd2_gmac.c174 #define RX_DESC_NUM 1024 macro
216 struct sk_buff *rx_skb[RX_DESC_NUM];
352 hix5hd2_set_desc_depth(priv, RX_DESC_NUM, TX_DESC_NUM); in hix5hd2_hw_init()
425 num = CIRC_SPACE(start, end, RX_DESC_NUM); in hix5hd2_rx_refill()
447 pos = dma_ring_incr(pos, RX_DESC_NUM); in hix5hd2_rx_refill()
469 num = CIRC_CNT(end, start, RX_DESC_NUM); in hix5hd2_rx()
505 pos = dma_ring_incr(pos, RX_DESC_NUM); in hix5hd2_rx()
654 for (i = 0; i < RX_DESC_NUM; i++) { in hix5hd2_free_dma_desc_rings()
863 priv->rx_fq.count = RX_DESC_NUM; in hix5hd2_init_hw_desc_queue()
864 priv->rx_bq.count = RX_DESC_NUM; in hix5hd2_init_hw_desc_queue()
/linux-4.1.27/Documentation/devicetree/bindings/net/
Dhisilicon-hip04-net.txt12 channel, recv channel start from channel * number (RX_DESC_NUM)
24 Each controller's recv channel start from channel * number (RX_DESC_NUM).