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Searched refs:SZ_256 (Results 1 – 18 of 18) sorted by relevance

/linux-4.1.27/arch/arm/mach-imx/
Dmm-imx27.c88 mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); in imx27_soc_init()
89 mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); in imx27_soc_init()
90 mxc_register_gpio("imx21-gpio", 2, MX27_GPIO3_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); in imx27_soc_init()
91 mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); in imx27_soc_init()
92 mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); in imx27_soc_init()
93 mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); in imx27_soc_init()
Dmm-imx21.c87 mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); in imx21_soc_init()
88 mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); in imx21_soc_init()
89 mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); in imx21_soc_init()
90 mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); in imx21_soc_init()
91 mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); in imx21_soc_init()
92 mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); in imx21_soc_init()
Dmm-imx1.c56 mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256, in imx1_soc_init()
58 mxc_register_gpio("imx1-gpio", 1, MX1_GPIO2_BASE_ADDR, SZ_256, in imx1_soc_init()
60 mxc_register_gpio("imx1-gpio", 2, MX1_GPIO3_BASE_ADDR, SZ_256, in imx1_soc_init()
62 mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256, in imx1_soc_init()
/linux-4.1.27/arch/arm/mach-s3c64xx/
Ddev-uart.c34 [0] = DEFINE_RES_MEM(S3C_PA_UART0, SZ_256),
39 [0] = DEFINE_RES_MEM(S3C_PA_UART1, SZ_256),
44 [0] = DEFINE_RES_MEM(S3C_PA_UART2, SZ_256),
49 [0] = DEFINE_RES_MEM(S3C_PA_UART3, SZ_256),
Ddev-audio.c56 [0] = DEFINE_RES_MEM(S3C64XX_PA_IIS0, SZ_256),
77 [0] = DEFINE_RES_MEM(S3C64XX_PA_IIS1, SZ_256),
94 [0] = DEFINE_RES_MEM(S3C64XX_PA_IISV4, SZ_256),
144 [0] = DEFINE_RES_MEM(S3C64XX_PA_PCM0, SZ_256),
165 [0] = DEFINE_RES_MEM(S3C64XX_PA_PCM1, SZ_256),
198 [0] = DEFINE_RES_MEM(S3C64XX_PA_AC97, SZ_256),
/linux-4.1.27/arch/arm/mach-omap1/
Dmcbsp.c101 .end = OMAP7XX_MCBSP1_BASE + SZ_256,
128 .end = OMAP7XX_MCBSP2_BASE + SZ_256,
178 .end = OMAP1510_MCBSP1_BASE + SZ_256,
205 .end = OMAP1510_MCBSP2_BASE + SZ_256,
232 .end = OMAP1510_MCBSP3_BASE + SZ_256,
285 .end = OMAP1610_MCBSP1_BASE + SZ_256,
312 .end = OMAP1610_MCBSP2_BASE + SZ_256,
339 .end = OMAP1610_MCBSP3_BASE + SZ_256,
/linux-4.1.27/arch/arm/mach-tegra/
Diomap.h71 #define TEGRA_UARTC_SIZE SZ_256
74 #define TEGRA_UARTD_SIZE SZ_256
77 #define TEGRA_UARTE_SIZE SZ_256
80 #define TEGRA_PMC_SIZE SZ_256
/linux-4.1.27/arch/arm/mach-omap2/
Domap_hwmod_2xxx_3xxx_interconnect_data.c122 .pa_end = 0x48098000 + SZ_256 - 1,
131 .pa_end = 0x4809a000 + SZ_256 - 1,
140 .pa_end = 0x480b8000 + SZ_256 - 1,
/linux-4.1.27/arch/arm/plat-samsung/
Ddevs.c113 [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
832 [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256),
847 [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256),
943 [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
974 [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
1102 [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
1147 [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
1190 [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
/linux-4.1.27/include/linux/
Dsizes.h19 #define SZ_256 0x00000100 macro
/linux-4.1.27/arch/arm/mach-imx/devices/
Dplatform-mx2-emma.c15 .iosize = SZ_256, \
/linux-4.1.27/arch/sh/boards/
Dboard-apsh4ad0a.c33 .end = 0xA4000000 + SZ_256 - 1,
Dboard-apsh4a3a.c81 .end = 0xA4000000 + SZ_256 - 1,
/linux-4.1.27/arch/arm/mach-zynq/
Dcommon.c161 .length = SZ_256,
/linux-4.1.27/arch/sh/boards/mach-sdk7786/
Dsetup.c53 .end = 0x07ffff00 + SZ_256 - 1,
/linux-4.1.27/arch/sh/drivers/pci/
Dpcie-sh7786.c369 pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1, in pcie_init()
385 pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0); in pcie_init()
/linux-4.1.27/drivers/clocksource/
Dqcom-timer.c295 base = ioremap(addr, SZ_256); in msm_timer_map()
/linux-4.1.27/drivers/irqchip/
Dirq-gic-v3-its.c76 #define ITS_ITT_ALIGN SZ_256