Searched refs:TX_READY (Results 1 – 3 of 3) sorted by relevance
41 @ Clear TX_READY by writing to the UARTDM_CR register
111 #define TX_READY 0x02 macro285 if ((inb(HOST_CTRL_IO(io_base)) & TX_READY) != 0) { in host_write_unsafe()
516 XSIR_GET_BITS(status, SIR0_STATUS, TX_READY)) in amd_xgbe_phy_serdes_complete_ratechange()