Searched refs:UCR1_RRDYEN (Results 1 – 1 of 1) sorted by relevance
80 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ macro409 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); in imx_stop_rx()730 temp &= ~(UCR1_RRDYEN); in imx_dma_rxint()877 temp |= UCR1_RRDYEN; in imx_rx_dma_done()1144 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; in imx_startup()1216 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); in imx_shutdown()1378 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), in imx_set_termios()1508 temp |= UCR1_UARTEN | UCR1_RRDYEN; in imx_poll_init()1654 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); in imx_console_write()