Searched refs:clk_zero (Results 1 – 1 of 1) sorted by relevance
23 u32 clk_zero; member80 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()149 temp += ((timing->clk_zero >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc()165 timing->clk_pre, timing->clk_post, timing->clk_zero, in dsi_dphy_timing_calc()213 DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_28nm_phy_enable()218 if (timing->clk_zero & BIT(8)) in dsi_28nm_phy_enable()