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Searched refs:cntval_mask (Results 1 – 8 of 8) sorted by relevance

/linux-4.1.27/arch/tile/kernel/
Dperf_event.c75 u64 cntval_mask; /* counter width mask */ member
336 .cntval_mask = (1ULL << 32) - 1,
581 write_counter(idx, (u64)(-left) & tile_pmu->cntval_mask); in tile_event_set_period()
/linux-4.1.27/arch/x86/kernel/cpu/
Dperf_event_p6.c225 .cntval_mask = (1ULL << 32) - 1,
Dperf_event_knc.c305 .cntval_mask = (1ULL << 40) - 1,
Dperf_event_amd.c638 .cntval_mask = (1ULL << 48) - 1,
Dperf_event.c1120 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); in x86_perf_event_set_period()
1129 (u64)(-left) & x86_pmu.cntval_mask); in x86_perf_event_set_period()
1721 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); in init_hw_perf_events()
Dperf_event.h514 u64 cntval_mask; member
Dperf_event_p4.c1322 .cntval_mask = ARCH_P4_CNTRVAL_MASK,
Dperf_event_intel.c3024 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in intel_pmu_init()
3370 x86_pmu.max_period = x86_pmu.cntval_mask; in intel_pmu_init()