Searched refs:csrows (Results 1 – 23 of 23) sorted by relevance
| /linux-4.1.27/drivers/edac/ |
| D | edac_mc.c | 117 mci->nr_csrows, mci->csrows); in edac_mc_dump_mci()
220 if (mci->csrows) { in _edac_mc_free()
222 csr = mci->csrows[row]; in _edac_mc_free()
232 kfree(mci->csrows); in _edac_mc_free()
348 mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL); in edac_mc_alloc()
349 if (!mci->csrows) in edac_mc_alloc()
352 csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL); in edac_mc_alloc()
355 mci->csrows[row] = csr; in edac_mc_alloc()
385 chan = mci->csrows[row]->channels[chn]; in edac_mc_alloc()
735 struct csrow_info *csrow = mci->csrows[i]; in edac_mc_add_mc_with_groups()
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| D | pasemi_edac.c | 114 mci->csrows[cs]->first_page, 0, 0, in pasemi_edac_process_error_info()
121 mci->csrows[cs]->first_page, 0, 0, in pasemi_edac_process_error_info()
144 csrow = mci->csrows[index]; in pasemi_edac_init_csrows()
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| D | amd76x_edac.c | 149 mci->csrows[row]->first_page, 0, 0, in amd76x_process_error_info()
164 mci->csrows[row]->first_page, 0, 0, in amd76x_process_error_info()
197 csrow = mci->csrows[index]; in amd76x_init_csrows()
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| D | cell_edac.c | 37 struct csrow_info *csrow = mci->csrows[0]; in cell_edac_count_ce()
60 struct csrow_info *csrow = mci->csrows[0]; in cell_edac_count_ue()
130 struct csrow_info *csrow = mci->csrows[0]; in cell_edac_init_csrows()
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| D | i82975x_edac.c | 311 chan = (mci->csrows[row]->nr_channels == 1) ? 0 : info->eap & 1; in i82975x_process_error_info()
314 (1 << mci->csrows[row]->channels[chan]->dimm->grain)); in i82975x_process_error_info()
393 csrow = mci->csrows[index]; in i82975x_init_csrows()
419 dimm = mci->csrows[index]->channels[chan]->dimm; in i82975x_init_csrows()
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| D | edac_mc_sysfs.c | 431 csrow = mci->csrows[i]; in edac_create_csrow_objects()
434 err = edac_create_csrow_object(mci, mci->csrows[i], i); in edac_create_csrow_objects()
446 csrow = mci->csrows[i]; in edac_create_csrow_objects()
449 put_device(&mci->csrows[i]->dev); in edac_create_csrow_objects()
461 csrow = mci->csrows[i]; in edac_delete_csrow_objects()
464 device_unregister(&mci->csrows[i]->dev); in edac_delete_csrow_objects()
632 struct csrow_info *ri = mci->csrows[row]; in mci_reset_counters_store()
764 struct csrow_info *csrow = mci->csrows[csrow_idx]; in mci_size_mb_show()
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| D | i82860_edac.c | 119 dimm = mci->csrows[row]->channels[0]->dimm; in i82860_process_error_info()
164 csrow = mci->csrows[index]; in i82860_init_csrows()
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| D | i3000_edac.c | 239 multi_chan = mci->csrows[0]->nr_channels - 1; in i3000_process_error_info()
396 struct csrow_info *csrow = mci->csrows[i]; in i3000_probe1()
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| D | i82875p_edac.c | 230 multi_chan = mci->csrows[0]->nr_channels - 1; in i82875p_process_error_info()
364 csrow = mci->csrows[index]; in i82875p_init_csrows()
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| D | tile_edac.c | 87 struct csrow_info *csrow = mci->csrows[0]; in tile_edac_init_csrows()
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| D | cpc925_edac.c | 350 csrow = mci->csrows[index]; in cpc925_init_csrows()
465 if (mci->csrows[rank]->first_page == 0) { in cpc925_mc_get_pfn()
473 pa = mci->csrows[rank]->first_page << PAGE_SHIFT; in cpc925_mc_get_pfn()
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| D | r82600_edac.c | 233 csrow = mci->csrows[index]; in r82600_init_csrows()
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| D | i82443bxgx_edac.c | 200 csrow = mci->csrows[index]; in i82443bxgx_init_csrows()
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| D | synopsys_edac.c | 369 csi = mci->csrows[row]; in synps_edac_init_csrows()
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| D | x38_edac.c | 377 struct csrow_info *csrow = mci->csrows[i]; in x38_probe1()
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| D | e7xxx_edac.c | 381 csrow = mci->csrows[index]; in e7xxx_init_csrows()
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| D | mpc85xx_edac.c | 856 csrow = mci->csrows[row_index]; in mpc85xx_mc_check()
976 csrow = mci->csrows[index]; in mpc85xx_init_csrows()
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| D | ppc4xx_edac.c | 923 struct csrow_info *csi = mci->csrows[row]; in ppc4xx_edac_init_csrows()
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| D | mv64x60_edac.c | 673 csrow = mci->csrows[0]; in mv64x60_init_csrows()
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| D | e752x_edac.c | 1098 csrow = mci->csrows[remap_csrow_index(mci, index)]; in e752x_init_csrows()
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| D | amd64_edac.c | 2432 csrow = mci->csrows[i]; in init_csrows()
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| /linux-4.1.27/Documentation/ |
| D | edac.txt | 152 be multiple csrows and multiple channels.
154 Memory controllers allow for several csrows, with 8 csrows being a typical value.
155 Yet, the actual number of csrows depends on the electrical "loading"
184 are channel 1. Notice that there are two csrows possible on a
185 physical DIMM. These csrows are allocated their csrow assignment
187 is placed in each Channel, the csrows cross both DIMMs.
644 The minimum known unity is DIMMs. There are no information about csrows.
645 As EDAC API maps the minimum unity is csrows, the driver sequencially
646 maps channel/dimm into different csrows.
756 What happens here is that errors on different csrows, but at the same
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| /linux-4.1.27/include/linux/ |
| D | edac.h | 703 struct csrow_info **csrows; member
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