| /linux-4.1.27/drivers/gpu/drm/nouveau/ |
| D | nouveau_dp.c | 35 u8 *dpcd) in nouveau_dp_probe_oui() argument
40 if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in nouveau_dp_probe_oui()
59 u8 *dpcd = nv_encoder->dp.dpcd; in nouveau_dp_detect() local
66 ret = nv_rdaux(auxch, DP_DPCD_REV, dpcd, 8); in nouveau_dp_detect()
70 nv_encoder->dp.link_bw = 27000 * dpcd[1]; in nouveau_dp_detect()
71 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; in nouveau_dp_detect()
74 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]); in nouveau_dp_detect()
87 nouveau_dp_probe_oui(dev, auxch, dpcd); in nouveau_dp_detect()
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| D | nouveau_encoder.h | 58 u8 dpcd[8]; member
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | dport.c | 85 outp->dpcd[DPCD_RC02] & in dp_set_link_config()
98 if (outp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP) in dp_set_link_config()
172 if (outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL]) in dp_link_train_update()
173 mdelay(outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4); in dp_link_train_update()
234 if (outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED) in dp_link_train_eq()
338 outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED; in nvkm_dp_train()
339 if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) { in nvkm_dp_train()
340 outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT; in nvkm_dp_train()
341 outp->dpcd[2] |= outp->base.info.dpconf.link_nr; in nvkm_dp_train()
343 if (outp->dpcd[1] > outp->base.info.dpconf.link_bw) in nvkm_dp_train()
[all …]
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| D | outpdp.c | 82 if (outp->dpcd[DPCD_RC00_DPCD_REV] == 0x00) { in nvkm_output_dp_train()
83 outp->dpcd[DPCD_RC01_MAX_LINK_RATE] = in nvkm_output_dp_train()
85 outp->dpcd[DPCD_RC02] = in nvkm_output_dp_train()
132 outp->dpcd, sizeof(outp->dpcd)); in nvkm_output_dp_detect()
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| D | outpdp.h | 17 u8 dpcd[16]; member
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| /linux-4.1.27/include/drm/ |
| D | drm_dp_helper.h | 584 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
585 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
618 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate()
620 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); in drm_dp_max_link_rate()
624 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_lane_count()
626 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in drm_dp_max_lane_count()
630 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_enhanced_frame_cap()
632 return dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_enhanced_frame_cap()
633 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); in drm_dp_enhanced_frame_cap()
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| D | drm_dp_mst_helper.h | 435 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
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| /linux-4.1.27/drivers/gpu/drm/radeon/ |
| D | atombios_dp.c | 307 const u8 dpcd[DP_DPCD_SIZE], in radeon_dp_get_dp_link_config()
313 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in radeon_dp_get_dp_link_config()
314 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in radeon_dp_get_dp_link_config()
375 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in radeon_dp_probe_oui()
397 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in radeon_dp_getdpcd()
399 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), in radeon_dp_getdpcd()
400 dig_connector->dpcd); in radeon_dp_getdpcd()
407 dig_connector->dpcd[0] = 0; in radeon_dp_getdpcd()
467 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_set_link_config()
494 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_mode_valid_helper()
[all …]
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| D | radeon_dp_mst.c | 527 dig_connector->dpcd, adjusted_mode->clock, in radeon_mst_mode_fixup()
684 if (dig_connector->dpcd[DP_DPCD_REV] < 0x12) in radeon_dp_mst_probe()
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| D | radeon_mode.h | 488 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
756 const u8 *dpcd,
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| /linux-4.1.27/drivers/gpu/drm/ |
| D | drm_dp_helper.c | 118 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { in drm_dp_link_train_clock_recovery_delay()
119 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) in drm_dp_link_train_clock_recovery_delay()
122 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); in drm_dp_link_train_clock_recovery_delay()
126 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { in drm_dp_link_train_channel_eq_delay()
127 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) in drm_dp_link_train_channel_eq_delay()
130 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); in drm_dp_link_train_channel_eq_delay()
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| D | drm_dp_mst_topology.c | 2022 ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_mst_topology_mgr_set_mst()
2028 if (!drm_dp_get_vc_payload_bw(mgr->dpcd[1], in drm_dp_mst_topology_mgr_set_mst()
2029 mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK, in drm_dp_mst_topology_mgr_set_mst()
2127 sret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_mst_topology_mgr_resume()
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| /linux-4.1.27/drivers/gpu/drm/gma500/ |
| D | cdv_intel_dp.c | 266 uint8_t dpcd[4]; member
329 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { in cdv_intel_dp_max_lane_count()
330 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; in cdv_intel_dp_max_lane_count()
345 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; in cdv_intel_dp_max_link_bw()
1079 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && in cdv_intel_dp_mode_set()
1080 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { in cdv_intel_dp_mode_set()
1115 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in cdv_intel_dp_sink_dpms()
1709 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd, in cdv_dp_detect()
1710 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) in cdv_dp_detect()
1712 if (intel_dp->dpcd[DP_DPCD_REV] != 0) in cdv_dp_detect()
[all …]
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| /linux-4.1.27/drivers/gpu/drm/i915/ |
| D | intel_dp.c | 131 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; in intel_dp_max_link_bw()
158 sink_max = drm_dp_max_lane_count(intel_dp->dpcd); in intel_dp_max_lane_count()
1563 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_dp_prepare()
1577 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_dp_prepare()
2127 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_sink_dpms()
3555 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_dp_start_link_train()
3582 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); in intel_dp_start_link_train()
3662 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); in intel_dp_complete_link_train()
3775 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, in intel_dp_get_dpcd()
3776 sizeof(intel_dp->dpcd)) < 0) in intel_dp_get_dpcd()
[all …]
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| D | intel_dp_mst.c | 54 lane_count = drm_dp_max_lane_count(intel_dp->dpcd); in intel_dp_mst_compute_config()
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| D | intel_drv.h | 625 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; member
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| D | intel_ddi.c | 2030 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_ddi_prepare_link_retrain()
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| D | i915_debugfs.c | 2573 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); in intel_dp_info()
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| /linux-4.1.27/drivers/gpu/drm/msm/edp/ |
| D | edp_ctrl.c | 106 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
638 drm_dp_link_train_clock_recovery_delay(ctrl->dpcd); in edp_start_link_train_1()
695 drm_dp_link_train_channel_eq_delay(ctrl->dpcd); in edp_start_link_train_2()
773 drm_dp_link_train_channel_eq_delay(ctrl->dpcd); in edp_clear_training_pattern()
1215 if (drm_dp_dpcd_read(ctrl->drm_aux, DP_DPCD_REV, ctrl->dpcd, in msm_edp_ctrl_panel_connected()
1218 memset(ctrl->dpcd, 0, DP_RECEIVER_CAP_SIZE); in msm_edp_ctrl_panel_connected()
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