Searched refs:eventsel (Results 1 – 11 of 11) sorted by relevance
24 u8 eventsel; member206 if (arch_events[i].eventsel == event_select in find_arch_event()217 static void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel) in reprogram_gp_counter() argument222 if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL) in reprogram_gp_counter()225 pmc->eventsel = eventsel; in reprogram_gp_counter()229 if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_enabled(pmc)) in reprogram_gp_counter()232 event_select = eventsel & ARCH_PERFMON_EVENTSEL_EVENT; in reprogram_gp_counter()233 unit_mask = (eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; in reprogram_gp_counter()235 if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE | in reprogram_gp_counter()247 config = eventsel & X86_RAW_EVENT_MASK; in reprogram_gp_counter()[all …]
148 static inline int amd_pmu_addr_offset(int index, bool eventsel) in amd_pmu_addr_offset() argument155 if (eventsel) in amd_pmu_addr_offset()168 if (eventsel) in amd_pmu_addr_offset()631 .eventsel = MSR_K7_EVNTSEL0,674 x86_pmu.eventsel = MSR_F15H_PERF_CTL; in amd_core_pmu_init()
505 unsigned eventsel; member507 int (*addr_offset)(int index, bool eventsel);687 return x86_pmu.eventsel + (x86_pmu.addr_offset ? in x86_pmu_config_addr()
209 .eventsel = MSR_P6_EVNTSEL0,
296 .eventsel = MSR_KNC_EVNTSEL0,
1308 .eventsel = MSR_P4_BPU_CCCR0,
2712 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,2750 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
32 - a raw PMU event (eventsel+umask) in the form of rNNN where NNN is a
42 event (eventsel+umask) in the form of rNNN where NNN is a
33 - a raw PMU event (eventsel+umask) in the form of rNNN where NNN is a
318 u64 eventsel; member