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Searched refs:gpc_base (Results 1 – 3 of 3) sorted by relevance

/linux-4.1.27/arch/arm/mach-imx/
Dgpc.c53 static void __iomem *gpc_base; variable
60 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR); in imx_gpc_set_arm_power_up_timing()
66 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR); in imx_gpc_set_arm_power_down_timing()
71 writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN); in imx_gpc_set_arm_power_in_lpm()
76 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; in imx_gpc_pre_suspend()
91 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; in imx_gpc_post_resume()
119 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; in imx_gpc_mask_all()
131 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; in imx_gpc_restore_all()
143 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; in imx_gpc_hwirq_unmask()
154 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; in imx_gpc_hwirq_mask()
[all …]
Dpm-imx5.c69 static void __iomem *gpc_base; variable
91 arm_srpgcr = __raw_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) & in mx5_cpu_lp_set()
93 empgc0 = __raw_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) & in mx5_cpu_lp_set()
95 empgc1 = __raw_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) & in mx5_cpu_lp_set()
132 __raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR); in mx5_cpu_lp_set()
133 __raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR); in mx5_cpu_lp_set()
139 __raw_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); in mx5_cpu_lp_set()
140 __raw_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); in mx5_cpu_lp_set()
162 __raw_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); in mx5_suspend_enter()
163 __raw_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); in mx5_suspend_enter()
[all …]
Dpm-imx6.c192 struct imx6_pm_base gpc_base; member
508 ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat); in imx6q_suspend_init()
541 iounmap(&pm_info->gpc_base.vbase); in imx6q_suspend_init()