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Searched refs:ltq_cgu_r32 (Results 1 – 3 of 3) sorted by relevance

/linux-4.1.27/arch/mips/lantiq/xway/
Dclk.c23 #define DDR_HZ ram_clocks[ltq_cgu_r32(CGU_SYS) & 0x3]
36 if (ltq_cgu_r32(CGU_SYS) & 0x40) in ltq_danube_fpi_hz()
43 switch (ltq_cgu_r32(CGU_SYS) & 0xc) { in ltq_danube_cpu_hz()
57 unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3; in ltq_danube_pp32_hz()
80 if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2) in ltq_ar9_sys_hz()
89 if (ltq_cgu_r32(CGU_SYS) & BIT(0)) in ltq_ar9_fpi_hz()
96 if (ltq_cgu_r32(CGU_SYS) & BIT(2)) in ltq_ar9_cpu_hz()
107 cpu_sel = (ltq_cgu_r32(CGU_SYS_VR9) >> 4) & 0xf; in ltq_vr9_cpu_hz()
148 ocp_sel = ltq_cgu_r32(CGU_SYS_VR9) & 0x3; in ltq_vr9_fpi_hz()
177 unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 3; in ltq_vr9_pp32_hz()
Dsysctrl.c111 ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr); in cgu_enable()
118 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr); in cgu_disable()
146 unsigned int val = ltq_cgu_r32(ifccr); in pci_enable()
170 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr); in pci_ext_enable()
178 ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr); in pci_ext_disable()
192 unsigned int val = ltq_cgu_r32(ifccr); in clkout_enable()
358 if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) in ltq_soc_init()
/linux-4.1.27/arch/mips/include/asm/mach-lantiq/xway/
Dlantiq_soc.h59 #define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) macro