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Searched refs:mode_reg (Results 1 – 37 of 37) sorted by relevance

/linux-4.1.27/drivers/clk/qcom/
Dclk-pll.c44 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
53 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
65 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
74 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
84 regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_disable()
89 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0); in clk_pll_disable()
166 regmap_read(pll->clkr.regmap, pll->mode_reg, &mode); in clk_pll_set_rate()
238 regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0); in clk_pll_set_fsm_mode()
244 regmap_update_bits(regmap, pll->mode_reg, mask, val); in clk_pll_set_fsm_mode()
247 regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_ENA, in clk_pll_set_fsm_mode()
Dclk-pll.h52 u32 mode_reg; member
Dlcc-ipq806x.c39 .mode_reg = 0x0,
Dmmcc-msm8974.c193 .mode_reg = 0x0000,
220 .mode_reg = 0x0040,
247 .mode_reg = 0x4100,
262 .mode_reg = 0x0080,
Dgcc-ipq806x.c40 .mode_reg = 0x30c0,
67 .mode_reg = 0x3160,
94 .mode_reg = 0x3140,
121 .mode_reg = 0x31c0,
Dmmcc-apq8084.c228 .mode_reg = 0x0000,
255 .mode_reg = 0x0040,
282 .mode_reg = 0x4100,
297 .mode_reg = 0x0080,
313 .mode_reg = 0x0080,
Dlcc-msm8960.c39 .mode_reg = 0x0,
Dgcc-msm8916.c200 .mode_reg = 0x21000,
227 .mode_reg = 0x20000,
254 .mode_reg = 0x4a000,
281 .mode_reg = 0x23000,
Dgcc-msm8974.c71 .mode_reg = 0x0000,
134 .mode_reg = 0x0040,
161 .mode_reg = 0x1dc0,
Dgcc-apq8084.c115 .mode_reg = 0x0000,
178 .mode_reg = 0x0040,
205 .mode_reg = 0x1dc0,
Dgcc-msm8960.c40 .mode_reg = 0x3160,
67 .mode_reg = 0x3140,
94 .mode_reg = 0x31c0,
Dmmcc-msm8960.c92 .mode_reg = 0x31c,
108 .mode_reg = 0x338,
Dgcc-msm8660.c40 .mode_reg = 0x3140,
/linux-4.1.27/drivers/clk/spear/
Dclk-vco-pll.c202 mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK; in clk_vco_recalc_rate()
244 val = readl_relaxed(vco->mode_reg); in clk_vco_set_rate()
247 writel_relaxed(val, vco->mode_reg); in clk_vco_set_rate()
277 unsigned long flags, void __iomem *mode_reg, void __iomem in clk_register_vco_pll() argument
288 if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg || in clk_register_vco_pll()
307 vco->mode_reg = mode_reg; in clk_register_vco_pll()
319 parent_name, 0, mode_reg, PLL_ENABLE, 0, lock); in clk_register_vco_pll()
Dclk.h95 void __iomem *mode_reg; member
125 unsigned long flags, void __iomem *mode_reg, void __iomem
/linux-4.1.27/drivers/atm/
DuPD98402.c104 unsigned char mode_reg; in set_loopback() local
106 mode_reg = GET(MDR) & ~(uPD98402_MDR_TPLP | uPD98402_MDR_ALP | in set_loopback()
112 mode_reg |= uPD98402_MDR_TPLP; in set_loopback()
115 mode_reg |= uPD98402_MDR_ALP; in set_loopback()
124 mode_reg |= uPD98402_MDR_RPLP; in set_loopback()
129 PUT(mode_reg,MDR); in set_loopback()
/linux-4.1.27/drivers/media/i2c/
Dlm3646.c77 u8 mode_reg; member
90 REG_ENABLE, flash->mode_reg | MODE_SHDN); in lm3646_mode_ctrl()
93 REG_ENABLE, flash->mode_reg | MODE_TORCH); in lm3646_mode_ctrl()
96 REG_ENABLE, flash->mode_reg | MODE_FLASH); in lm3646_mode_ctrl()
305 flash->mode_reg = reg_val & 0xfc; in lm3646_init_device()
Dmsp3400-kthreads.c91 int mode_reg; member
238 msp_write_dem(client, 0x0083, data->mode_reg); in msp3400c_set_mode()
/linux-4.1.27/drivers/gpu/drm/nouveau/dispnv04/
Ddfp.c95 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; in nv04_dfp_disable()
122 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; in nv04_dfp_update_fp_control()
137 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; in nv04_dfp_update_fp_control()
206 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv04_dfp_prepare_sel_clk()
250 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; in nv04_dfp_prepare()
287 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_dfp_mode_set()
462 nv04_display(dev)->mode_reg.crtc_reg[head].fp_control = in nv04_dfp_commit()
553 nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); in nv04_lvds_dpms()
554 nv04_display(dev)->mode_reg.sel_clk &= ~0xf0; in nv04_lvds_dpms()
556 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); in nv04_lvds_dpms()
Dtvnv04.c76 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv04_tv_dpms()
104 struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head]; in nv04_tv_bind()
143 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_tv_mode_set()
Dcrtc.c61 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_digital_vibrance()
76 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_image_sharpening()
118 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv_crtc_calc_state_ext()
242 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_vga()
467 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_regs()
658 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); in nv_crtc_mode_set()
668 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv_crtc_save()
730 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); in nv_crtc_commit()
774 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; in nv_crtc_gamma_load()
781 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); in nv_crtc_gamma_load()
[all …]
Dcursor.c42 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_cursor_set_offset()
Ddisp.h79 struct nv04_mode_state mode_reg; member
Dtvnv17.c411 uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[ in nv17_tv_prepare()
472 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head]; in nv17_tv_mode_set()
Dhw.h377 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]; in nv_show_cursor()
Dtvmodesnv17.c548 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head]; in nv17_ctv_update_rescaler()
/linux-4.1.27/drivers/dma/sh/
Drcar-hpbdma.c108 void __iomem *mode_reg; member
170 iowrite32(data, hpbdev->mode_reg); in asyncmdr_write()
175 return ioread32(hpbdev->mode_reg); in asyncmdr_read()
577 hpbdev->mode_reg = devm_ioremap_resource(&pdev->dev, mode); in hpb_dmae_probe()
578 if (IS_ERR(hpbdev->mode_reg)) in hpb_dmae_probe()
579 return PTR_ERR(hpbdev->mode_reg); in hpb_dmae_probe()
/linux-4.1.27/drivers/mfd/
Dmenelaus.c454 u8 mode_reg; member
483 ret = menelaus_write_reg(vtg->mode_reg, mode); in menelaus_set_voltage()
577 .mode_reg = MENELAUS_LDO_CTRL3,
606 .mode_reg = MENELAUS_LDO_CTRL4,
646 .mode_reg = MENELAUS_DCDC_CTRL2,
654 .mode_reg = MENELAUS_DCDC_CTRL3,
691 .mode_reg = MENELAUS_LDO_CTRL7,
721 .mode_reg = MENELAUS_LDO_CTRL6,
/linux-4.1.27/drivers/net/ethernet/
Ddnet.c178 u32 mode_reg, ctl_reg; in dnet_handle_link_change() local
184 mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG); in dnet_handle_link_change()
204 mode_reg |= DNET_INTERNAL_MODE_GBITEN; in dnet_handle_link_change()
208 mode_reg &= ~DNET_INTERNAL_MODE_GBITEN; in dnet_handle_link_change()
223 mode_reg |= in dnet_handle_link_change()
226 mode_reg &= in dnet_handle_link_change()
239 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg); in dnet_handle_link_change()
/linux-4.1.27/include/video/
Dw100fb.h64 unsigned long mode_reg; member
/linux-4.1.27/arch/powerpc/platforms/powermac/
Dlow_i2c.c403 u8 mode_reg = host->speed; in kw_i2c_xfer() local
411 mode_reg |= KW_I2C_MODE_STANDARD; in kw_i2c_xfer()
416 mode_reg |= KW_I2C_MODE_STANDARDSUB; in kw_i2c_xfer()
421 mode_reg |= KW_I2C_MODE_COMBINED; in kw_i2c_xfer()
429 kw_write_reg(reg_mode, mode_reg | (bus->channel << 4)); in kw_i2c_xfer()
438 if ((mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_STANDARDSUB in kw_i2c_xfer()
439 || (mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_COMBINED) in kw_i2c_xfer()
/linux-4.1.27/drivers/mmc/host/
Datmel-mci.c215 u32 mode_reg; member
767 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE); in atmci_pdc_set_single_buf()
955 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE); in atmci_prepare_data_pdc()
1160 atmci_writel(host, ATMCI_MR, host->mode_reg); in atmci_start_request()
1310 if (!host->mode_reg) { in atmci_set_ios()
1342 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1) in atmci_set_ios()
1352 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv); in atmci_set_ios()
1361 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF); in atmci_set_ios()
1372 atmci_writel(host, ATMCI_MR, host->mode_reg); in atmci_set_ios()
1393 if (host->mode_reg) { in atmci_set_ios()
[all …]
/linux-4.1.27/drivers/regulator/
Dab8500.c78 u8 mode_reg; member
359 reg = info->mode_reg; in ab8500_regulator_set_mode()
457 info->mode_bank, info->mode_reg, &val); in ab8500_regulator_get_mode()
1153 .mode_reg = 0x54,
1174 .mode_reg = 0x54,
1686 .mode_reg = 0x83,
1707 .mode_reg = 0x83,
/linux-4.1.27/drivers/tty/serial/
Dxilinx_uartps.c634 unsigned int ctrl_reg, mode_reg; in cdns_uart_set_termios() local
702 mode_reg = readl(port->membase + CDNS_UART_MR_OFFSET); in cdns_uart_set_termios()
742 cval |= mode_reg & 1; in cdns_uart_set_termios()
/linux-4.1.27/drivers/scsi/
Dnsp32.c1451 unsigned char mode_reg; in nsp32_show_info() local
1468 mode_reg = nsp32_index_read1(base, CHIP_MODE); in nsp32_show_info()
1472 seq_printf(m, "Power Management: %s\n", (mode_reg & OPTF) ? "yes" : "no"); in nsp32_show_info()
1474 …seq_printf(m, "OEM: %ld, %s\n", (mode_reg & (OEM0|OEM1)), nsp32_model[model]… in nsp32_show_info()
/linux-4.1.27/arch/arm/mach-pxa/
Dhx4700.c495 .mode_reg = 0x00250000,
/linux-4.1.27/drivers/video/fbdev/
Dw100fb.c1411 writel(bm_mem->mode_reg, remapped_regs + mmBM_MEM_MODE_REG); in w100_setup_memory()