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Searched refs:mpll (Results 1 – 34 of 34) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Dradeon_clocks.c67 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_legacy_get_memory_clock() local
73 fb_div *= mpll->reference_freq; in radeon_legacy_get_memory_clock()
107 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_read_clocks_OF() local
145 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
146 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
182 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_get_clock_info() local
214 if (mpll->reference_div < 2) in radeon_get_clock_info()
215 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
229 mpll->reference_freq = 1432; in radeon_get_clock_info()
234 mpll->reference_freq = 2700; in radeon_get_clock_info()
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Dradeon_combios.c737 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_combios_get_clock_info() local
778 mpll->reference_freq = RBIOS16(pll_info + 0x26); in radeon_combios_get_clock_info()
779 mpll->reference_div = RBIOS16(pll_info + 0x28); in radeon_combios_get_clock_info()
780 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); in radeon_combios_get_clock_info()
781 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); in radeon_combios_get_clock_info()
784 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); in radeon_combios_get_clock_info()
785 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); in radeon_combios_get_clock_info()
788 mpll->pll_in_min = 40; in radeon_combios_get_clock_info()
789 mpll->pll_in_max = 500; in radeon_combios_get_clock_info()
Dradeon_atombios.c1145 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_atom_get_clock_info() local
1224 mpll->reference_freq = in radeon_atom_get_clock_info()
1227 mpll->reference_freq = in radeon_atom_get_clock_info()
1229 mpll->reference_div = 0; in radeon_atom_get_clock_info()
1231 mpll->pll_out_min = in radeon_atom_get_clock_info()
1233 mpll->pll_out_max = in radeon_atom_get_clock_info()
1237 if (mpll->pll_out_min == 0) { in radeon_atom_get_clock_info()
1239 mpll->pll_out_min = 64800; in radeon_atom_get_clock_info()
1241 mpll->pll_out_min = 20000; in radeon_atom_get_clock_info()
1244 mpll->pll_in_min = in radeon_atom_get_clock_info()
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Drv740_dpm.c252 u32 reference_clock = rdev->clock.mpll.reference_freq; in rv740_populate_mclk_value()
Drv730_dpm.c172 u32 reference_clock = rdev->clock.mpll.reference_freq; in rv730_populate_mclk_value()
Dcypress_dpm.c443 u32 ref_clk = rdev->clock.mpll.reference_freq; in cypress_map_clkf_to_ibias()
559 u32 reference_clock = rdev->clock.mpll.reference_freq; in cypress_populate_mclk_value()
Drv6xx_dpm.c656 u32 ref_clk = rdev->clock.mpll.reference_freq; in rv6xx_program_mclk_spread_spectrum_parameters()
Drv770_dpm.c404 u32 reference_clock = rdev->clock.mpll.reference_freq; in rv770_populate_mclk_value()
Dradeon.h263 struct radeon_pll mpll; member
Dni_dpm.c2242 u32 reference_clock = rdev->clock.mpll.reference_freq; in ni_populate_mclk_value()
Dsi_dpm.c4856 u32 reference_clock = rdev->clock.mpll.reference_freq; in si_populate_mclk_value()
Dci_dpm.c2801 u32 reference_clock = rdev->clock.mpll.reference_freq; in ci_calculate_mclk_params()
/linux-4.1.27/arch/arm/mach-s3c24xx/
Dcpufreq-utils.c64 if (!IS_ERR(cfg->mpll)) in s3c2410_set_fvco()
65 clk_set_rate(cfg->mpll, cfg->pll.frequency); in s3c2410_set_fvco()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c285 bool mpll = Preg == 0x4020; in setPLL_double_lowregs() local
288 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | in setPLL_double_lowregs()
303 if (mpll) { in setPLL_double_lowregs()
319 Pval |= mpll ? 1 << 12 : 1 << 8; in setPLL_double_lowregs()
323 if (mpll) { in setPLL_double_lowregs()
337 if (mpll) { in setPLL_double_lowregs()
346 if (mpll) { in setPLL_double_lowregs()
/linux-4.1.27/drivers/clk/samsung/
Dclk-s3c2410.c40 mpll, upll, enumerator
199 [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
265 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
388 s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl; in s3c2410_common_clk_init()
402 s3c244x_common_plls[mpll].rate_table = in s3c2410_common_clk_init()
Dclk-exynos5410.c58 apll, cpll, mpll, enumerator
177 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
Dclk-s3c2412.c34 mpll, upll, enumerator
149 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
Dclk-s3c2443.c48 mpll, epll, enumerator
226 [mpll] = PLL(pll_6552_s3c2416, 0, "mpll", "mpllref",
280 [mpll] = PLL(pll_3000, 0, "mpll", "mpllref",
Dclk-s5pv210.c75 mpll, enumerator
761 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
773 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
Dclk-s3c64xx.c62 apll, mpll, epll, enumerator
370 [mpll] = PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
Dclk-exynos5250.c108 apll, mpll, cpll, epll, vpll, gpll, bpll, enumerator
737 [mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
Dclk-exynos4.c152 apll, mpll, epll, vpll, enumerator
1340 [mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1351 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
Dclk-exynos5420.c147 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator
1242 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramnv50.c67 struct nvbios_pll mpll; in nv50_ram_calc() local
130 ret = nvbios_pll_parse(bios, 0x004008, &mpll); in nv50_ram_calc()
131 mpll.vco2.max_freq = 0; in nv50_ram_calc()
133 ret = nv04_pll_calc(nv_subdev(pfb), &mpll, freq, in nv50_ram_calc()
145 ram_mask(hwsq, 0x004008, 0x81ff0000, 0x80000000 | (mpll.bias_p << 19) | in nv50_ram_calc()
/linux-4.1.27/arch/arm/mach-imx/
Dclk-imx35.c54 ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg, enumerator
92 clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MX35_CCM_MPCTL); in mx35_clocks_init()
95 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); in mx35_clocks_init()
Dclk-imx31.c37 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
59 clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL); in mx31_clocks_init()
Dclk-imx25.c68 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
98 clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL)); in __mx25_clocks_init()
/linux-4.1.27/Documentation/devicetree/bindings/clock/
Dimx31-clock.txt18 mpll 3
Dimx35-clock.txt16 mpll 1
Dimx25-clock.txt17 mpll 2
/linux-4.1.27/arch/arm/plat-samsung/include/plat/
Dcpu-freq-core.h122 struct clk *mpll; member
/linux-4.1.27/Documentation/devicetree/bindings/media/
Dexynos4-fimc-is.txt19 "mpll", "sysreg", "isp", "drc", "fd", "mcuisp", "uart",
/linux-4.1.27/arch/arm/boot/dts/
Dexynos4x12.dtsi249 "ppmuispmx", "mpll", "isp",
/linux-4.1.27/drivers/cpufreq/
Ds3c24xx-cpufreq.c143 cfg->mpll = _clk_mpll; in s3c_cpufreq_setfvco()