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Searched refs:nv_mask (Results 1 – 101 of 101) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dhdmig84.c57 nv_mask(priv, 0x6165a4 + hoff, 0x40000000, 0x00000000); in g84_hdmi_ctrl()
58 nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
59 nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
64 nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
70 nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000001); in g84_hdmi_ctrl()
73 nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
77 nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000001); in g84_hdmi_ctrl()
79 nv_mask(priv, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ in g84_hdmi_ctrl()
80 nv_mask(priv, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ in g84_hdmi_ctrl()
81 nv_mask(priv, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ in g84_hdmi_ctrl()
[all …]
Dhdmigt215.c58 nv_mask(priv, 0x61c5a4 + soff, 0x40000000, 0x00000000); in gt215_hdmi_ctrl()
59 nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
60 nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
65 nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
71 nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000001); in gt215_hdmi_ctrl()
74 nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
78 nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000001); in gt215_hdmi_ctrl()
80 nv_mask(priv, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ in gt215_hdmi_ctrl()
81 nv_mask(priv, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ in gt215_hdmi_ctrl()
82 nv_mask(priv, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ in gt215_hdmi_ctrl()
[all …]
Dhdmigk104.c57 nv_mask(priv, 0x616798 + hoff, 0x40000000, 0x00000000); in gk104_hdmi_ctrl()
58 nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000000); in gk104_hdmi_ctrl()
59 nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000000); in gk104_hdmi_ctrl()
64 nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000000); in gk104_hdmi_ctrl()
70 nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000001); in gk104_hdmi_ctrl()
73 nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000000); in gk104_hdmi_ctrl()
75 nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000001); in gk104_hdmi_ctrl()
81 nv_mask(priv, 0x616798 + hoff, 0x401f007f, ctrl); in gk104_hdmi_ctrl()
Dhdmigf110.c56 nv_mask(priv, 0x616798 + hoff, 0x40000000, 0x00000000); in gf110_hdmi_ctrl()
57 nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000000); in gf110_hdmi_ctrl()
58 nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000000); in gf110_hdmi_ctrl()
63 nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000000); in gf110_hdmi_ctrl()
69 nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000001); in gf110_hdmi_ctrl()
72 nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000000); in gf110_hdmi_ctrl()
74 nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000001); in gf110_hdmi_ctrl()
77 nv_mask(priv, 0x616798 + hoff, 0x401f007f, ctrl); in gf110_hdmi_ctrl()
Dhdagf110.c55 nv_mask(priv, 0x616618 + hoff, 0x8000000c, 0x80000001); in gf110_hda_eld()
58 nv_mask(priv, 0x616548 + hoff, 0x00000070, 0x00000000); in gf110_hda_eld()
63 nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000003); in gf110_hda_eld()
66 nv_mask(priv, 0x616618 + hoff, 0x80000001, 0x80000000); in gf110_hda_eld()
69 nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000000 | !!size); in gf110_hda_eld()
Dhdagt215.c52 nv_mask(priv, 0x61c1e0 + soff, 0x8000000d, 0x80000001); in gt215_hda_eld()
59 nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000003); in gt215_hda_eld()
62 nv_mask(priv, 0x61c1e0 + soff, 0x80000001, 0x80000000); in gt215_hda_eld()
65 nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000000 | !!size); in gt215_hda_eld()
Dgf110.c50 nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000000 << index); in gf110_disp_chan_uevent_fini()
59 nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000001 << index); in gf110_disp_chan_uevent_init()
104 nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid); in gf110_disp_dmac_init()
110 nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00000010, 0x00000010); in gf110_disp_dmac_init()
132 nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00001010, 0x00001000); in gf110_disp_dmac_fini()
133 nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00000003, 0x00000000); in gf110_disp_dmac_fini()
142 nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000); in gf110_disp_dmac_fini()
143 nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000); in gf110_disp_dmac_fini()
304 nv_mask(priv, 0x6100a0, 0x00000001, 0x00000001); in gf110_disp_core_init()
310 nv_mask(priv, 0x610490, 0x00000010, 0x00000010); in gf110_disp_core_init()
[all …]
Dsorgm204.c48 nv_mask(priv, 0x612308 + soff, 0x0000001f, 0x00000000 | data); in gm204_sor_magic()
50 nv_mask(priv, 0x612388 + soff, 0x0000001f, 0x00000010 | data); in gm204_sor_magic()
66 nv_mask(priv, 0x61c110 + soff, 0x0f0f0f0f, data); in gm204_sor_dp_pattern()
68 nv_mask(priv, 0x61c12c + soff, 0x0f0f0f0f, data); in gm204_sor_dp_pattern()
83 nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask); in gm204_sor_dp_lnk_pwr()
84 nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000); in gm204_sor_dp_lnk_pwr()
Ddacnv50.c57 nv_mask(priv, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat); in nv50_dac_power()
82 nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80150000); in nv50_dac_sense()
88 loadval = nv_mask(priv, 0x61a00c + doff, 0xffffffff, 0x00000000); in nv50_dac_sense()
90 nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80550000); in nv50_dac_sense()
Dsorg94.c57 nv_mask(priv, 0x61c10c + loff, 0x0f000000, pattern << 24); in g94_sor_dp_pattern()
72 nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask); in g94_sor_dp_lnk_pwr()
73 nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000); in g94_sor_dp_lnk_pwr()
93 nv_mask(priv, 0x614300 + soff, 0x000c0000, clksor); in g94_sor_dp_lnk_ctl()
94 nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl); in g94_sor_dp_lnk_ctl()
Dnv50.c93 nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000000 << index); in nv50_disp_chan_uevent_fini()
102 nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000001 << index); in nv50_disp_chan_uevent_init()
269 nv_mask(priv, 0x610028, 0x00010000 << chid, 0x00010000 << chid); in nv50_disp_dmac_init()
275 nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010); in nv50_disp_dmac_init()
297 nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000); in nv50_disp_dmac_fini()
298 nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000); in nv50_disp_dmac_fini()
307 nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid); in nv50_disp_dmac_fini()
528 nv_mask(priv, 0x610028, 0x00010000, 0x00010000); in nv50_disp_core_init()
532 nv_mask(priv, 0x610200, 0x00800000, 0x00800000); in nv50_disp_core_init()
534 nv_mask(priv, 0x610200, 0x00600000, 0x00600000); in nv50_disp_core_init()
[all …]
Dsorgf110.c51 nv_mask(priv, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern); in gf110_sor_dp_pattern()
69 nv_mask(priv, 0x612300 + soff, 0x007c0000, clksor); in gf110_sor_dp_lnk_ctl()
70 nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl); in gf110_sor_dp_lnk_ctl()
Dsornv50.c52 nv_mask(priv, 0x61c004 + soff, 0x80000001, 0x80000000 | stat); in nv50_sor_power()
Dpiornv50.c166 nv_mask(priv, 0x61e004 + soff, 0x80000101, 0x80000000 | ctrl); in nv50_pior_power()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dgk104.c32 nv_mask(pmu, 0x000200, 0x00001000, 0x00000000); in gk104_pmu_pgob()
34 nv_mask(pmu, 0x000200, 0x08000000, 0x08000000); in gk104_pmu_pgob()
37 nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000002); in gk104_pmu_pgob()
38 nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001); in gk104_pmu_pgob()
39 nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000); in gk104_pmu_pgob()
41 nv_mask(pmu, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000); in gk104_pmu_pgob()
44 nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000000); in gk104_pmu_pgob()
45 nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001); in gk104_pmu_pgob()
46 nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000); in gk104_pmu_pgob()
48 nv_mask(pmu, 0x000200, 0x08000000, 0x00000000); in gk104_pmu_pgob()
[all …]
Dgk110.c57 nv_mask(pmu, 0x000200, 0x00001000, 0x00000000); in gk110_pmu_pgob()
59 nv_mask(pmu, 0x000200, 0x08000000, 0x08000000); in gk110_pmu_pgob()
62 nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000002); in gk110_pmu_pgob()
63 nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001); in gk110_pmu_pgob()
64 nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000); in gk110_pmu_pgob()
66 nv_mask(pmu, 0x0206b4, 0x00000000, 0x00000000); in gk110_pmu_pgob()
72 nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000000); in gk110_pmu_pgob()
73 nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001); in gk110_pmu_pgob()
74 nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000); in gk110_pmu_pgob()
76 nv_mask(pmu, 0x000200, 0x08000000, 0x00000000); in gk110_pmu_pgob()
[all …]
Dgt215.c31 nv_mask(pmu, 0x022210, 0x00000001, 0x00000000); in gt215_pmu_init()
32 nv_mask(pmu, 0x022210, 0x00000001, 0x00000001); in gt215_pmu_init()
Dbase.c202 nv_mask(pmu, 0x000200, 0x00002000, 0x00000000); in _nvkm_pmu_init()
203 nv_mask(pmu, 0x000200, 0x00002000, 0x00002000); in _nvkm_pmu_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv05.c77 nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); in nv05_devinit_meminit()
88 nv_mask(priv, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]); in nv05_devinit_meminit()
91 nv_mask(priv, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE); in nv05_devinit_meminit()
93 nv_mask(priv, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20); in nv05_devinit_meminit()
94 nv_mask(priv, NV04_PFB_CFG1, 0, 1); in nv05_devinit_meminit()
101 nv_mask(priv, NV04_PFB_BOOT_0, in nv05_devinit_meminit()
110 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, in nv05_devinit_meminit()
115 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, in nv05_devinit_meminit()
119 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, in nv05_devinit_meminit()
Dnv04.c52 nv_mask(priv, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF); in nv04_devinit_meminit()
54 nv_mask(priv, NV04_PFB_BOOT_0, ~0, in nv04_devinit_meminit()
65 nv_mask(priv, NV04_PFB_BOOT_0, in nv04_devinit_meminit()
68 nv_mask(priv, NV04_PFB_DEBUG_0, in nv04_devinit_meminit()
75 nv_mask(priv, NV04_PFB_BOOT_0, in nv04_devinit_meminit()
81 nv_mask(priv, NV04_PFB_BOOT_0, in nv04_devinit_meminit()
88 nv_mask(priv, NV04_PFB_BOOT_0, in nv04_devinit_meminit()
92 nv_mask(priv, NV04_PFB_BOOT_0, in nv04_devinit_meminit()
96 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, in nv04_devinit_meminit()
100 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, in nv04_devinit_meminit()
[all …]
Dnv50.c60 nv_mask(priv, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1); in nv50_devinit_pll_set()
61 nv_mask(priv, info.reg + 8, 0x7fff00ff, (P << 28) | in nv50_devinit_pll_set()
65 nv_mask(priv, info.reg + 0, 0x01ff0000, (P << 22) | in nv50_devinit_pll_set()
71 nv_mask(priv, info.reg + 0, 0x00070000, (P << 16)); in nv50_devinit_pll_set()
Dnv20.c51 nv_mask(priv, NV04_PFB_CFG0, 0, mask); in nv20_devinit_meminit()
60 nv_mask(priv, NV04_PFB_CFG0, mask, 0); in nv20_devinit_meminit()
Dnv10.c59 nv_mask(priv, NV04_PFB_CFG0, 0x30, mem_width[i]); in nv10_devinit_meminit()
93 nv_mask(priv, NV04_PFB_CFG0, 0x1000, 0); in nv10_devinit_meminit()
Dgm204.c121 nv_mask(priv, 0x000200, 0x00002000, 0x00000000); in gm204_devinit_post()
122 nv_mask(priv, 0x000200, 0x00002000, 0x00002000); in gm204_devinit_post()
Dgt215.c52 nv_mask(priv, info.reg + 4, 0x003fffff, in gt215_devinit_pll_set()
Dgf100.c53 nv_mask(priv, info.reg + 0x0c, 0x00000000, 0x00000100); in gf100_devinit_pll_set()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
Dgk104.c37 nv_mask(priv, 0x122128 + (i * 0x0800), 0x00000200, 0x00000000); in gk104_ibus_intr_hub()
47 nv_mask(priv, 0x124128 + (i * 0x0800), 0x00000200, 0x00000000); in gk104_ibus_intr_rop()
57 nv_mask(priv, 0x128128 + (i * 0x0800), 0x00000200, 0x00000000); in gk104_ibus_intr_gpc()
102 nv_mask(priv, 0x122318, 0x0003ffff, 0x00001000); in gk104_ibus_init()
103 nv_mask(priv, 0x12231c, 0x0003ffff, 0x00000200); in gk104_ibus_init()
104 nv_mask(priv, 0x122310, 0x0003ffff, 0x00000800); in gk104_ibus_init()
105 nv_mask(priv, 0x122348, 0x0003ffff, 0x00000100); in gk104_ibus_init()
106 nv_mask(priv, 0x1223b0, 0x0003ffff, 0x00000fff); in gk104_ibus_init()
107 nv_mask(priv, 0x122348, 0x0003ffff, 0x00000200); in gk104_ibus_init()
108 nv_mask(priv, 0x122358, 0x0003ffff, 0x00002880); in gk104_ibus_init()
Dgk20a.c32 nv_mask(priv, 0x137250, 0x3f, 0); in gk20a_ibus_init_priv_ring()
34 nv_mask(priv, 0x000200, 0x20, 0); in gk20a_ibus_init_priv_ring()
36 nv_mask(priv, 0x000200, 0x20, 0x20); in gk20a_ibus_init_priv_ring()
55 nv_mask(priv, 0x12004c, 0x2, 0x2); in gk20a_ibus_intr()
Dgf100.c37 nv_mask(priv, 0x122128 + (i * 0x0400), 0x00000200, 0x00000000); in gf100_ibus_intr_hub()
47 nv_mask(priv, 0x124128 + (i * 0x0400), 0x00000200, 0x00000000); in gf100_ibus_intr_rop()
57 nv_mask(priv, 0x128128 + (i * 0x0400), 0x00000200, 0x00000000); in gf100_ibus_intr_gpc()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgt215.c303 nv_mask(clk, 0x020060, 0x00070000, 0x00000000); in gt215_clk_pre()
304 nv_mask(clk, 0x002504, 0x00000001, 0x00000001); in gt215_clk_pre()
328 nv_mask(clk, 0x002504, 0x00000001, 0x00000000); in gt215_clk_post()
329 nv_mask(clk, 0x020060, 0x00070000, 0x00040000); in gt215_clk_post()
335 nv_mask(priv, src, 0x00000100, 0x00000000); in disable_clk_src()
336 nv_mask(priv, src, 0x00000001, 0x00000000); in disable_clk_src()
353 nv_mask(priv, src1, 0x00000101, 0x00000101); in prog_pll()
354 nv_mask(priv, ctrl, 0x00000008, 0x00000008); in prog_pll()
358 nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk); in prog_pll()
360 nv_mask(priv, ctrl, 0x00000015, 0x00000015); in prog_pll()
[all …]
Dgk104.c354 nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv); in gk104_clk_prog_0()
362 nv_mask(priv, 0x137100, (1 << clk), 0x00000000); in gk104_clk_prog_1_0()
369 nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000); in gk104_clk_prog_1_1()
377 nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000); in gk104_clk_prog_2()
378 nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000); in gk104_clk_prog_2()
381 nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001); in gk104_clk_prog_2()
383 nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004); in gk104_clk_prog_2()
392 nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv); in gk104_clk_prog_3()
394 nv_mask(priv, 0x137250 + (clk * 0x04), 0x0000003f, info->mdiv); in gk104_clk_prog_3()
402 nv_mask(priv, 0x137100, (1 << clk), info->ssel); in gk104_clk_prog_4_0()
[all …]
Dgf100.c337 nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv); in gf100_clk_prog_0()
345 nv_mask(priv, 0x137100, (1 << clk), 0x00000000); in gf100_clk_prog_1()
355 nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000); in gf100_clk_prog_2()
356 nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000); in gf100_clk_prog_2()
359 nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001); in gf100_clk_prog_2()
361 nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004); in gf100_clk_prog_2()
371 nv_mask(priv, 0x137100, (1 << clk), info->ssel); in gf100_clk_prog_3()
380 nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv); in gf100_clk_prog_4()
Dgk20a.c280 nv_mask(priv, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, in gk20a_pllg_slide()
282 nv_mask(priv, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT, in gk20a_pllg_slide()
286 nv_mask(priv, GPCPLL_NDIV_SLOWDOWN, in gk20a_pllg_slide()
311 nv_mask(priv, GPCPLL_NDIV_SLOWDOWN, in gk20a_pllg_slide()
327 nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); in _gk20a_pllg_enable()
334 nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); in _gk20a_pllg_disable()
367 nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, in _gk20a_pllg_program_mnp()
412 nv_mask(priv, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); in _gk20a_pllg_program_mnp()
454 nv_mask(priv, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); in gk20a_pllg_disable()
620 nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); in gk20a_clk_init()
Dnv40.c195 nv_mask(priv, 0x00c040, 0x00000333, 0x00000000); in nv40_clk_prog()
197 nv_mask(priv, 0x004000, 0xc0070100, priv->npll_ctrl); in nv40_clk_prog()
198 nv_mask(priv, 0x004008, 0xc007ffff, priv->spll); in nv40_clk_prog()
200 nv_mask(priv, 0x00c040, 0x00000333, priv->ctrl); in nv40_clk_prog()
Dmcp77.c308 mast = nv_mask(clk, 0xc054, 0x03400e70, 0x03400640); in mcp77_clk_prog()
314 nv_mask(clk, 0x4028, 0x00070000, priv->cctrl); in mcp77_clk_prog()
331 nv_mask(clk, 0x4020, 0x00070000, 0x00000000); in mcp77_clk_prog()
335 nv_mask(clk, 0x4020, 0x00070000, priv->sctrl); in mcp77_clk_prog()
368 nv_mask(clk, 0x4028, 0x80000000, 0x00000000); in mcp77_clk_prog()
373 nv_mask(clk, 0x4020, 0x80000000, 0x00000000); in mcp77_clk_prog()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxgk104.c877 nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001); in gk104_grctx_generate_unkn()
878 nv_mask(priv, 0x41980c, 0x00000010, 0x00000010); in gk104_grctx_generate_unkn()
879 nv_mask(priv, 0x41be08, 0x00000004, 0x00000004); in gk104_grctx_generate_unkn()
880 nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000); in gk104_grctx_generate_unkn()
881 nv_mask(priv, 0x405800, 0x08000000, 0x08000000); in gk104_grctx_generate_unkn()
882 nv_mask(priv, 0x419c00, 0x00000008, 0x00000008); in gk104_grctx_generate_unkn()
947 nv_mask(priv, 0x408850, 0x0000000f, fbp_count); /* zrop */ in gk104_grctx_generate_rop_active_fbps()
948 nv_mask(priv, 0x408958, 0x0000000f, fbp_count); /* crop */ in gk104_grctx_generate_rop_active_fbps()
982 nv_mask(priv, 0x419f78, 0x00000001, 0x00000000); in gk104_grctx_generate_main()
989 nv_mask(priv, 0x418800, 0x00200000, 0x00200000); in gk104_grctx_generate_main()
[all …]
Dctxgf108.c770 nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001); in gf108_grctx_generate_unkn()
771 nv_mask(priv, 0x41980c, 0x00000010, 0x00000010); in gf108_grctx_generate_unkn()
772 nv_mask(priv, 0x419814, 0x00000004, 0x00000004); in gf108_grctx_generate_unkn()
773 nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000); in gf108_grctx_generate_unkn()
774 nv_mask(priv, 0x405800, 0x08000000, 0x08000000); in gf108_grctx_generate_unkn()
775 nv_mask(priv, 0x419c00, 0x00000008, 0x00000008); in gf108_grctx_generate_unkn()
Dctxgm204.c942 nv_mask(priv, 0x408850, 0x0000000f, fbp_count); /* zrop */ in gm204_grctx_generate_rop_active_fbps()
943 nv_mask(priv, 0x408958, 0x0000000f, fbp_count); /* crop */ in gm204_grctx_generate_rop_active_fbps()
1019 nv_mask(priv, 0x418e94, 0xffffffff, 0xc4230000); in gm204_grctx_generate_main()
1020 nv_mask(priv, 0x418e4c, 0xffffffff, 0x70000000); in gm204_grctx_generate_main()
Dnv40.c163 nv_mask(priv, 0x400720, 0x00000001, 0x00000000); in nv40_gr_context_fini()
169 nv_mask(priv, 0x400310, 0x00000020, 0x00000020); in nv40_gr_context_fini()
170 nv_mask(priv, 0x400304, 0x00000001, 0x00000001); in nv40_gr_context_fini()
178 nv_mask(priv, 0x40032c, 0x01000000, 0x00000000); in nv40_gr_context_fini()
182 nv_mask(priv, 0x400330, 0x01000000, 0x00000000); in nv40_gr_context_fini()
184 nv_mask(priv, 0x400720, 0x00000001, 0x00000001); in nv40_gr_context_fini()
315 nv_mask(priv, 0x402000, 0, 0); in nv40_gr_intr()
Dnv10.c563 nv_mask(priv, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100); in nv17_gr_mthd_lma_enable()
564 nv_mask(priv, 0x4006b0, 0x08000000, 0x08000000); in nv17_gr_mthd_lma_enable()
908 nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13); in nv10_gr_load_dma_vtxbuf()
915 nv_mask(priv, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000); in nv10_gr_load_dma_vtxbuf()
916 nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); in nv10_gr_load_dma_vtxbuf()
917 nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); in nv10_gr_load_dma_vtxbuf()
956 nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); in nv10_gr_load_context()
957 nv_mask(priv, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000); in nv10_gr_load_context()
979 nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); in nv10_gr_unload_context()
1095 nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); in nv10_gr_context_fini()
[all …]
Dctxgm107.c991 nv_mask(priv, 0x419e00, 0x00808080, 0x00808080); in gm107_grctx_generate_main()
992 nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000); in gm107_grctx_generate_main()
993 nv_mask(priv, 0x419f80, 0x80000000, 0x80000000); in gm107_grctx_generate_main()
994 nv_mask(priv, 0x419f88, 0x80000000, 0x80000000); in gm107_grctx_generate_main()
Dgm204.c273 nv_mask(priv, 0x4188b0, 0x00040000, 0x00040000); in gm204_gr_init()
278 nv_mask(priv, 0x100cc4, 0x00040000, 0x00040000); in gm204_gr_init()
329 nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); in gm204_gr_init()
Dnv04.c1056 nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24); in nv04_gr_load_context()
1057 nv_mask(priv, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000); in nv04_gr_load_context()
1071 nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); in nv04_gr_unload_context()
1168 nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); in nv04_gr_context_fini()
1171 nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); in nv04_gr_context_fini()
1365 nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); in nv04_gr_init()
Dnv20.c124 nv_mask(priv, 0x400720, 0x00000001, 0x00000000); in nv20_gr_context_fini()
132 nv_mask(priv, 0x400148, 0xff000000, 0x1f000000); in nv20_gr_context_fini()
134 nv_mask(priv, 0x400720, 0x00000001, 0x00000001); in nv20_gr_context_fini()
Dgk104.c270 nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); in gk104_gr_init()
271 nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); in gk104_gr_init()
Dgm107.c391 nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); in gm107_gr_init()
Dnv50.c249 nv_mask(priv, 0x400500, 0x00000001, 0x00000000); in g84_gr_tlb_flush()
292 nv_mask(priv, 0x400500, 0x00000001, 0x00000001); in g84_gr_tlb_flush()
Dctxgf100.c1342 nv_mask(priv, 0x409b04, 0x80000000, 0x00000000); in gf100_grctx_generate()
Dgf100.c1481 nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); in gf100_gr_init()
1482 nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); in gf100_gr_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramnv40.c107 nv_mask(pfb, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */ in nv40_ram_prog()
111 nv_mask(pfb, 0x00c040, 0x0000c000, 0x00000000); in nv40_ram_prog()
118 nv_mask(pfb, 0x004044, 0xc0771100, ram->ctrl); in nv40_ram_prog()
119 nv_mask(pfb, 0x00402c, 0xc0771100, ram->ctrl); in nv40_ram_prog()
125 nv_mask(pfb, 0x004038, 0xc0771100, ram->ctrl); in nv40_ram_prog()
128 nv_mask(pfb, 0x004020, 0xc0771100, ram->ctrl); in nv40_ram_prog()
133 nv_mask(pfb, 0x00c040, 0x0000c000, 0x0000c000); in nv40_ram_prog()
137 nv_mask(pfb, 0x100210, 0x80000000, 0x80000000); in nv40_ram_prog()
Drammcp77.c85 nv_mask(pfb, 0x100c14, 0x00000000, 0x00000001); in mcp77_ram_init()
87 nv_mask(pfb, 0x100c14, 0x00000000, 0x00000002); in mcp77_ram_init()
89 nv_mask(pfb, 0x100c14, 0x00000000, 0x00010000); in mcp77_ram_init()
Dramgt215.c202 nv_mask(pfb, 0x100674, 0x0000ffff, 0x00000000); in gt215_link_train()
203 nv_mask(pfb, 0x1005e4, 0x0000ffff, 0x00000000); in gt215_link_train()
204 nv_mask(pfb, 0x100b0c, 0x000000ff, 0x00000000); in gt215_link_train()
242 nv_mask(pfb, 0x616308, 0x10, 0x10); in gt215_link_train()
243 nv_mask(pfb, 0x616b08, 0x10, 0x10); in gt215_link_train()
309 nv_mask(pfb, 0x10f800, 0x00000001, 0x00000001); in gt215_link_train_init()
866 nv_mask(pfb, 0x001534, 0x2, 0x2); in gt215_ram_prog()
871 nv_mask(pfb, 0x002504, 0x1, 0x0); in gt215_ram_prog()
872 nv_mask(pfb, 0x001534, 0x2, 0x0); in gt215_ram_prog()
874 nv_mask(pfb, 0x616308, 0x10, 0x10); in gt215_ram_prog()
[all …]
Dgk20a.c38 nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ in gk20a_fb_init()
Dnv40.c55 nv_mask(priv, 0x10033c, 0x00008000, 0x00000000); in nv40_fb_init()
Dramgk104.c1093 nv_mask(pfb, 0x10f468, mask, data); in gk104_ram_prog_0()
1099 nv_mask(pfb, 0x10f420, mask, data); in gk104_ram_prog_0()
1105 nv_mask(pfb, 0x10f430, mask, data); in gk104_ram_prog_0()
1111 nv_mask(pfb, 0x10f400, mask, data); in gk104_ram_prog_0()
1117 nv_mask(pfb, 0x10f410, mask, data); in gk104_ram_prog_0()
1127 nv_mask(pfb, 0x10f440, mask, data); in gk104_ram_prog_0()
1141 nv_mask(pfb, 0x10f444, mask, data); in gk104_ram_prog_0()
1342 nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4); in gk104_ram_init()
1351 nv_mask(pfb, 0x10f65c, 0x000000f0, save); in gk104_ram_init()
1352 nv_mask(pfb, 0x10f584, 0x11000000, 0x00000000); in gk104_ram_init()
[all …]
Dgf100.c65 nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ in gf100_fb_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dshadowrom.c44 nv_mask(bios, 0x001850, 0x00000001, 0x00000001); in prom_fini()
46 nv_mask(bios, 0x088050, 0x00000001, 0x00000001); in prom_fini()
56 nv_mask(bios, 0x001850, 0x00000001, 0x00000000); in prom_init()
58 nv_mask(bios, 0x088050, 0x00000001, 0x00000000); in prom_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dgf110.c64 nv_mask(therm, 0x00d610 + (line * 0x04), 0x000000c0, data); in gf110_fan_pwm_ctrl()
100 nv_mask(therm, 0x0200d8, 0x1fff, divs); /* keep the high bits */ in gf110_fan_pwm_set()
129 nv_mask(priv, 0x00e720, 0x00000003, 0x00000002); in gf110_therm_init()
131 nv_mask(priv, 0x00d79c, 0x000000ff, priv->base.fan->tach.line); in gf110_therm_init()
133 nv_mask(priv, 0x00e720, 0x00000001, 0x00000001); in gf110_therm_init()
135 nv_mask(priv, 0x00e720, 0x00000002, 0x00000000); in gf110_therm_init()
Dgt215.c57 nv_mask(priv, 0x00e720, 0x00000003, 0x00000002); in gt215_therm_init()
60 nv_mask(priv, 0x00e720, 0x001f0000, tach->line << 16); in gt215_therm_init()
61 nv_mask(priv, 0x00e720, 0x00000001, 0x00000001); in gt215_therm_init()
63 nv_mask(priv, 0x00e720, 0x00000002, 0x00000000); in gt215_therm_init()
Dnv40.c68 nv_mask(therm, 0x15b8, 0x80000000, 0); in nv40_sensor_setup()
117 if (line == 2) nv_mask(therm, 0x0010f0, 0x80000000, mask); in nv40_fan_pwm_ctrl()
118 else if (line == 9) nv_mask(therm, 0x0015f4, 0x80000000, mask); in nv40_fan_pwm_ctrl()
156 nv_mask(therm, 0x0010f0, 0x7fff7fff, (duty << 16) | divs); in nv40_fan_pwm_set()
160 nv_mask(therm, 0x0015f4, 0x7fffffff, duty); in nv40_fan_pwm_set()
Dnv50.c64 nv_mask(therm, ctrl, 0x00010001 << line, data << line); in nv50_fan_pwm_ctrl()
125 nv_mask(therm, 0x20010, 0x40000000, 0x0); in nv50_sensor_setup()
Dg84.c51 nv_mask(therm, 0x20008, 0x80008000, 0x80000000); in g84_sensor_setup()
52 nv_mask(therm, 0x2000c, 0x80000003, 0x00000000); in g84_sensor_setup()
Dgm107.c50 nv_mask(therm, 0x10eb10, 0x1fff, divs); /* keep the high bits */ in gm107_fan_pwm_set()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
Dpadgm204.c36 nv_mask(i2c, 0x00d97c + pad->addr, 0x00000001, 0x00000001); in gm204_i2c_pad_fini()
48 nv_mask(i2c, 0x00d970 + pad->addr, 0x0000c003, 0x00000002); in gm204_i2c_pad_init()
52 nv_mask(i2c, 0x00d970 + pad->addr, 0x0000c003, 0x0000c001); in gm204_i2c_pad_init()
56 nv_mask(i2c, 0x00d97c + pad->addr, 0x00000001, 0x00000000); in gm204_i2c_pad_init()
Dpadg94.c36 nv_mask(i2c, 0x00e50c + pad->addr, 0x00000001, 0x00000001); in g94_i2c_pad_fini()
48 nv_mask(i2c, 0x00e500 + pad->addr, 0x0000c003, 0x00000002); in g94_i2c_pad_init()
52 nv_mask(i2c, 0x00e500 + pad->addr, 0x0000c003, 0x0000c001); in g94_i2c_pad_init()
56 nv_mask(i2c, 0x00e50c + pad->addr, 0x00000001, 0x00000000); in g94_i2c_pad_init()
Dgm204.c32 nv_mask(aux, 0x00d954 + (ch * 0x50), 0x00310000, 0x00000000); in auxch_fini()
55 nv_mask(aux, 0x00d954 + (ch * 0x50), 0x00300000, ureq); in auxch_init()
132 stat = nv_mask(aux, 0x00d958 + (ch * 0x50), 0, 0); in gm204_aux()
Dnv4e.c42 nv_mask(priv, port->addr, 0x2f, state ? 0x21 : 0x01); in nv4e_i2c_drive_scl()
50 nv_mask(priv, port->addr, 0x1f, state ? 0x11 : 0x01); in nv4e_i2c_drive_sda()
Dg94.c62 nv_mask(aux, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000); in auxch_fini()
85 nv_mask(aux, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq); in auxch_init()
162 stat = nv_mask(aux, 0x00e4e8 + (ch * 0x50), 0, 0); in g94_aux()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
Dgf110.c48 nv_mask(gpio, 0x00d610 + (line * 4), 0xff, unk0); in gf110_gpio_reset()
50 nv_mask(gpio, 0x00d740 + (unk1 * 4), 0xff, line); in gf110_gpio_reset()
58 nv_mask(gpio, 0x00d610 + (line * 4), 0x00003000, data); in gf110_gpio_drive()
59 nv_mask(gpio, 0x00d604, 0x00000001, 0x00000001); /* update? */ in gf110_gpio_drive()
Dnv50.c52 nv_mask(gpio, reg, 0x00010001 << lsh, val << lsh); in nv50_gpio_reset()
77 nv_mask(gpio, reg, 3 << shift, (((dir ^ 1) << 1) | out) << shift); in nv50_gpio_drive()
Dnv10.c76 nv_mask(gpio, reg, mask << line, data << line); in nv10_gpio_drive()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
Dnv50.c35 nv_mask(pbus, 0x001098, 0x00000008, 0x00000000); in nv50_bus_hwsq_exec()
39 nv_mask(pbus, 0x001098, 0x00000018, 0x00000018); in nv50_bus_hwsq_exec()
73 nv_mask(pbus, 0x001140, stat, 0); in nv50_bus_intr()
Dg94.c35 nv_mask(pbus, 0x001098, 0x00000008, 0x00000000); in g94_bus_hwsq_exec()
40 nv_mask(pbus, 0x001098, 0x00000018, 0x00000018); in g94_bus_hwsq_exec()
Dgf100.c51 nv_mask(pbus, 0x001140, stat, 0x00000000); in gf100_bus_intr()
Dnv31.c62 nv_mask(pbus, 0x001140, stat, 0x00000000); in nv31_bus_intr()
Dnv04.c49 nv_mask(pbus, 0x001140, stat, 0x00000000); in nv04_bus_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv44.c69 nv_mask(priv, 0x00b32c, 0x00000001, 0x00000000); in nv44_mpeg_context_fini()
71 nv_mask(priv, 0x00b318, 0x80000000, 0x00000000); in nv44_mpeg_context_fini()
72 nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001); in nv44_mpeg_context_fini()
115 nv_mask(priv, 0x00b308, 0x00000000, 0x00000000); in nv44_mpeg_intr()
Dnv31.c77 nv_mask(priv, 0x00b300, 0x00010000, (dma0 & 0x00030000) ? 0x00010000 : 0); in nv31_mpeg_mthd_dma()
83 nv_mask(priv, 0x00b300, 0x00020000, (dma0 & 0x00030000) ? 0x00020000 : 0); in nv31_mpeg_mthd_dma()
213 nv_mask(priv, 0x00b308, 0x00000000, 0x00000000); in nv31_mpeg_intr()
282 nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001); in nv31_mpeg_init()
Dnv40.c50 nv_mask(priv, 0x00b300, 0x00030000, (dma0 & 0x00030000)); in nv40_mpeg_mthd_dma()
56 nv_mask(priv, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2); in nv40_mpeg_mthd_dma()
Dnv50.c203 nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001); in nv50_mpeg_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dgk104.c298 nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16); in gk104_fifo_chan_init()
302 nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); in gk104_fifo_chan_init()
304 nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); in gk104_fifo_chan_init()
318 nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800); in gk104_fifo_chan_fini()
448 nv_mask(priv, 0x002630, engm, engm); in gk104_fifo_recover_work()
459 nv_mask(priv, 0x002630, engm, 0x00000000); in gk104_fifo_recover_work()
472 nv_mask(priv, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800); in gk104_fifo_recover()
738 nv_mask(priv, 0x001704, 0x00000000, 0x00000000); in gk104_fifo_intr_fault()
741 nv_mask(priv, 0x001714, 0x00000000, 0x00000000); in gk104_fifo_intr_fault()
744 nv_mask(priv, 0x001718, 0x00000000, 0x00000000); in gk104_fifo_intr_fault()
[all …]
Dgf100.c283 nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000); in gf100_fifo_chan_fini()
423 nv_mask(priv, 0x002630, engm, engm); in gf100_fifo_recover_work()
434 nv_mask(priv, 0x002630, engm, 0x00000000); in gf100_fifo_recover_work()
447 nv_mask(priv, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); in gf100_fifo_recover()
624 nv_mask(priv, 0x001704, 0x00000000, 0x00000000); in gf100_fifo_intr_fault()
627 nv_mask(priv, 0x001714, 0x00000000, 0x00000000); in gf100_fifo_intr_fault()
630 nv_mask(priv, 0x001718, 0x00000000, 0x00000000); in gf100_fifo_intr_fault()
745 nv_mask(priv, 0x002628, ints, 0); in gf100_fifo_intr_engine_unit()
829 nv_mask(priv, 0x002140, stat, 0x00000000); in gf100_fifo_intr()
838 nv_mask(fifo, 0x002140, 0x80000000, 0x80000000); in gf100_fifo_uevent_init()
[all …]
Dnv04.c187 nv_mask(priv, NV04_PFIFO_MODE, mask, mask); in nv04_fifo_chan_init()
210 nv_mask(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0); in nv04_fifo_chan_fini()
212 nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); in nv04_fifo_chan_fini()
236 nv_mask(priv, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); in nv04_fifo_chan_fini()
311 nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); in nv04_fifo_pause()
340 nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); in nv04_fifo_start()
384 nv_mask(priv, NV04_PFIFO_CACHE1_ENGINE, engine, 0); in nv04_fifo_swmthd()
551 nv_mask(priv, NV03_PFIFO_INTR_EN_0, stat, 0x00000000); in nv04_fifo_intr()
Dnv40.c129 nv_mask(priv, 0x002500, 0x00000001, 0x00000000); in nv40_fifo_context_attach()
135 nv_mask(priv, 0x002500, 0x00000001, 0x00000001); in nv40_fifo_context_attach()
165 nv_mask(priv, 0x002500, 0x00000001, 0x00000000); in nv40_fifo_context_detach()
171 nv_mask(priv, 0x002500, 0x00000001, 0x00000001); in nv40_fifo_context_detach()
Dnv50.c132 me = nv_mask(priv, 0x00b860, 0x00000001, 0x00000001); in nv50_fifo_context_detach()
347 nv_mask(priv, 0x002600 + (chid * 4), 0x80000000, 0x00000000); in nv50_fifo_chan_fini()
507 nv_mask(priv, 0x000200, 0x00000100, 0x00000000); in nv50_fifo_init()
508 nv_mask(priv, 0x000200, 0x00000100, 0x00000100); in nv50_fifo_init()
Dg84.c106 save = nv_mask(priv, 0x002520, 0x0000003f, 1 << engn); in g84_fifo_context_detach()
425 nv_mask(fifo, 0x002140, 0x40000000, 0x40000000); in g84_fifo_uevent_init()
432 nv_mask(fifo, 0x002140, 0x40000000, 0x00000000); in g84_fifo_uevent_fini()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/
Dgf100.c51 nv_mask(priv, 0x17ea44, 0x0000000f, i); in gf100_ltc_zbc_clear_color()
61 nv_mask(priv, 0x17ea44, 0x0000000f, i); in gf100_ltc_zbc_clear_depth()
125 nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */ in gf100_ltc_init()
128 nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); in gf100_ltc_init()
Dgm107.c50 nv_mask(priv, 0x17e338, 0x0000000f, i); in gm107_ltc_zbc_clear_color()
60 nv_mask(priv, 0x17e338, 0x0000000f, i); in gm107_ltc_zbc_clear_depth()
104 nv_mask(priv, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); in gm107_ltc_init()
Dgk104.c40 nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); in gk104_ltc_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/
Dgf100.c41 fuse_enable = nv_mask(priv, 0x22400, 0x800, 0x800); in gf100_fuse_rd32()
42 unk = nv_mask(priv, 0x21000, 0x1, 0x1); in gf100_fuse_rd32()
Dnv50.c41 fuse_enable = nv_mask(priv, 0x1084, 0x800, 0x800); in nv50_fuse_rd32()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/core/
Dsubdev.c68 nv_mask(subdev, 0x000200, subdev->unit, 0x00000000); in nvkm_subdev_fini()
69 nv_mask(subdev, 0x000200, subdev->unit, subdev->unit); in nvkm_subdev_fini()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/pm/
Dgf100.c95 nv_mask(priv, 0x000200, 0x10000000, 0x00000000); in gf100_pm_fini()
96 nv_mask(priv, 0x000200, 0x10000000, 0x10000000); in gf100_pm_fini()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
Dgf100.c200 nv_mask(priv, 0x000200, 0x00000100, 0x00000000); in gf100_bar_init()
201 nv_mask(priv, 0x000200, 0x00000100, 0x00000100); in gf100_bar_init()
Dnv50.c238 nv_mask(priv, 0x000200, 0x00000100, 0x00000000); in nv50_bar_init()
239 nv_mask(priv, 0x000200, 0x00000100, 0x00000100); in nv50_bar_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sw/
Dnv04.c108 nv_mask(subdev, 0x000100, 0x80000000, 0x00000000); in nv04_sw_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/dispnv04/
Ddfp.c496 nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31); in nv04_dfp_update_backlight()
497 nv_mask(device, NV_PCRTC_GPIO_EXT, 3, 1); in nv04_dfp_update_backlight()
499 nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0); in nv04_dfp_update_backlight()
500 nv_mask(device, NV_PCRTC_GPIO_EXT, 3, 0); in nv04_dfp_update_backlight()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dnv41.c143 nv_mask(priv, 0x10008c, 0x00000100, 0x00000100); in nv41_mmu_init()
Dnv44.c231 nv_mask(priv, 0x10008c, 0x00000200, 0x00000200); in nv44_mmu_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/core/
Dsubdev.h113 nv_mask(void *obj, u32 addr, u32 mask, u32 data) in nv_mask() function
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/
Dxtensa.c70 nv_mask(xtensa, xtensa->addr + 0xd94, 0, xtensa->fifo_val); in _nvkm_xtensa_intr()