Searched refs:pll_con (Results 1 – 2 of 2) sorted by relevance
77 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll2126_recalc_rate() local80 pll_con = __raw_readl(pll->con_reg); in samsung_pll2126_recalc_rate()81 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK; in samsung_pll2126_recalc_rate()82 pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK; in samsung_pll2126_recalc_rate()83 sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK; in samsung_pll2126_recalc_rate()110 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll3000_recalc_rate() local113 pll_con = __raw_readl(pll->con_reg); in samsung_pll3000_recalc_rate()114 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK; in samsung_pll3000_recalc_rate()115 pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK; in samsung_pll3000_recalc_rate()116 sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK; in samsung_pll3000_recalc_rate()[all …]
298 u32 pll_con; in exynos4_clk_wait_for_pll() local300 pll_con = readl(reg_base + reg); in exynos4_clk_wait_for_pll()301 if (!(pll_con & PLL_ENABLED)) in exynos4_clk_wait_for_pll()304 while (!(pll_con & PLL_LOCKED)) { in exynos4_clk_wait_for_pll()306 pll_con = readl(reg_base + reg); in exynos4_clk_wait_for_pll()