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Searched refs:post_divider (Results 1 – 15 of 15) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Drv730_dpm.c53 u32 reference_divider, post_divider; in rv730_populate_sclk_value() local
65 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
68 post_divider = 1; in rv730_populate_sclk_value()
70 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()
93 u32 vco_freq = engine_clock * post_divider; in rv730_populate_sclk_value()
132 u32 post_divider, reference_divider; in rv730_populate_mclk_value() local
143 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value()
146 post_divider = 1; in rv730_populate_mclk_value()
168 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value()
Drv6xx_dpm.c151 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
153 step->post_divider = 1; in rv6xx_convert_clock_to_stepping()
155 step->vco_frequency = clock * step->post_divider; in rv6xx_convert_clock_to_stepping()
174 if (step->post_divider == 1) in rv6xx_output_stepping()
177 u32 lo_len = (step->post_divider - 2) / 2; in rv6xx_output_stepping()
178 u32 hi_len = step->post_divider - 2 - lo_len; in rv6xx_output_stepping()
200 next.post_divider = cur->post_divider; in rv6xx_next_vco_step()
214 return (cur->post_divider > target->post_divider) && in rv6xx_can_step_post_div()
215 ((cur->vco_frequency * target->post_divider) <= in rv6xx_can_step_post_div()
216 (target->vco_frequency * (cur->post_divider - 1))); in rv6xx_can_step_post_div()
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Drv6xx_dpm.h34 u32 post_divider; member
Dradeon_legacy_crtc.c742 uint32_t post_divider = 0; in radeon_set_pll() local
820 &reference_div, &post_divider); in radeon_set_pll()
823 if (post_div->divider == post_divider) in radeon_set_pll()
834 post_divider); in radeon_set_pll()
Drv770_dpm.c325 u32 post_divider, reference_divider, feedback_divider8; in rv770_calculate_fractional_mpll_feedback_divider() local
333 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
337 (8 * fyclk * reference_divider * post_divider) / reference_clock; in rv770_calculate_fractional_mpll_feedback_divider()
502 u32 reference_divider, post_divider; in rv770_populate_sclk_value() local
514 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2; in rv770_populate_sclk_value()
516 post_divider = 1; in rv770_populate_sclk_value()
518 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()
540 u32 vco_freq = engine_clock * post_divider; in rv770_populate_sclk_value()
Dradeon_mode.h603 u32 post_divider; member
Dci_dpm.c2643 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2651 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2684 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()
2717 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()
2749 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
2988 table->ACPILevel.SclkDid = (u8)dividers.post_divider; in ci_populate_smc_acpi_level()
3180 sclk->SclkDid = (u8)dividers.post_divider; in ci_calculate_sclk_params()
Dradeon_atombios.c2916 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; in radeon_atom_get_clock_dividers()
2933 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; in radeon_atom_get_clock_dividers()
Dcik.c9700 tmp |= dividers.post_divider; in cik_set_uvd_clock()
9747 tmp |= dividers.post_divider; in cik_set_vce_clocks()
/linux-4.1.27/drivers/video/fbdev/aty/
Dmach64_gx.c345 u32 post_divider; in aty_var_to_pll_18818() local
351 post_divider = 1; in aty_var_to_pll_18818()
362 post_divider *= 2; in aty_var_to_pll_18818()
373 switch (post_divider) { in aty_var_to_pll_18818()
393 pll->ics2595.post_divider = post_divider; in aty_var_to_pll_18818()
559 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_1703()
678 pll->ics2595.post_divider = 0; in aty_var_to_pll_8398()
796 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_408()
Dradeon_monitor.c199 rinfo->panel_info.post_divider = BIOS_IN8(tmp + 48); in radeon_get_panel_info_BIOS()
206 pr_debug("post_divider = %x\n", rinfo->panel_info.post_divider); in radeon_get_panel_info_BIOS()
670 rinfo->panel_info.post_divider = (ppll_divn >> 16) & 0x7; in radeon_fixup_panel_info()
676 (rinfo->panel_info.post_divider << 16), in radeon_fixup_panel_info()
Datyfb.h78 u32 post_divider; member
Daty128fb.c438 u32 post_divider; member
1364 div3 |= post_conv[pll->post_divider] << 16; in aty128_set_pll()
1402 pll->post_divider = post_dividers[i]; in aty128_var_to_pll()
1418 "vclk_per: %d\n", pll->post_divider, in aty128_var_to_pll()
Dradeonfb.h264 int post_divider; member
Dradeon_base.c1591 (rinfo->panel_info.post_divider << 16); in radeonfb_set_par()