Searched refs:rFPGA0_XA_HSSIParameter1 (Results 1 – 13 of 13) sorted by relevance
/linux-4.1.27/drivers/staging/rtl8723au/hal/ |
D | rtl8723a_phycfg.c | 212 rFPGA0_XA_HSSIParameter1, in phy_RFSerialRead() 488 pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; in phy_InitBBRFRegisterDefinition()
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D | HalDMOutSrc8723A_CE.c | 768 PHY_QueryBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, in _PHY_IQCalibrate()
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/linux-4.1.27/drivers/staging/rtl8188eu/hal/ |
D | bb_cfg.c | 639 reg[RF_PATH_A]->rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; in rtl88e_phy_init_bb_rf_register_definition()
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D | phy.c | 100 rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, BIT8); in rf_serial_read() 981 phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); in pi_mode_switch() 1112 dm_odm->RFCalibrateInfo.bRfPiEnable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, in phy_iq_calibrate()
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/linux-4.1.27/drivers/staging/rtl8192u/ |
D | r819xU_phyreg.h | 48 #define rFPGA0_XA_HSSIParameter1 0x820 macro
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D | r819xU_phy.c | 632 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; in rtl8192_InitBBRFRegDef()
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/linux-4.1.27/drivers/staging/rtl8192e/rtl8192e/ |
D | r819xE_phyreg.h | 52 #define rFPGA0_XA_HSSIParameter1 0x820 macro
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D | r8192E_phyreg.h | 65 #define rFPGA0_XA_HSSIParameter1 0x820 macro
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D | r8192E_phy.c | 440 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; in rtl8192_InitBBRFRegDef()
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/linux-4.1.27/drivers/staging/rtl8712/ |
D | rtl871x_mp_phy_regdef.h | 91 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
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/linux-4.1.27/drivers/staging/rtl8188eu/include/ |
D | Hal8188EPhyReg.h | 81 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
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D | rtw_mp_phy_regdef.h | 117 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
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/linux-4.1.27/drivers/staging/rtl8723au/include/ |
D | Hal8723APhyReg.h | 65 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
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