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Searched refs:rFPGA0_XA_HSSIParameter1 (Results 1 – 13 of 13) sorted by relevance

/linux-4.1.27/drivers/staging/rtl8723au/hal/
Drtl8723a_phycfg.c212 rFPGA0_XA_HSSIParameter1, in phy_RFSerialRead()
488 pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; in phy_InitBBRFRegisterDefinition()
DHalDMOutSrc8723A_CE.c768 PHY_QueryBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, in _PHY_IQCalibrate()
/linux-4.1.27/drivers/staging/rtl8188eu/hal/
Dbb_cfg.c639 reg[RF_PATH_A]->rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; in rtl88e_phy_init_bb_rf_register_definition()
Dphy.c100 rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, BIT8); in rf_serial_read()
981 phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); in pi_mode_switch()
1112 dm_odm->RFCalibrateInfo.bRfPiEnable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, in phy_iq_calibrate()
/linux-4.1.27/drivers/staging/rtl8192u/
Dr819xU_phyreg.h48 #define rFPGA0_XA_HSSIParameter1 0x820 macro
Dr819xU_phy.c632 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; in rtl8192_InitBBRFRegDef()
/linux-4.1.27/drivers/staging/rtl8192e/rtl8192e/
Dr819xE_phyreg.h52 #define rFPGA0_XA_HSSIParameter1 0x820 macro
Dr8192E_phyreg.h65 #define rFPGA0_XA_HSSIParameter1 0x820 macro
Dr8192E_phy.c440 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; in rtl8192_InitBBRFRegDef()
/linux-4.1.27/drivers/staging/rtl8712/
Drtl871x_mp_phy_regdef.h91 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
/linux-4.1.27/drivers/staging/rtl8188eu/include/
DHal8188EPhyReg.h81 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
Drtw_mp_phy_regdef.h117 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
/linux-4.1.27/drivers/staging/rtl8723au/include/
DHal8723APhyReg.h65 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro