Searched refs:rb_bufsz (Results 1 – 9 of 9) sorted by relevance
265 uint32_t rb_bufsz; in uvd_v1_0_start() local376 rb_bufsz = order_base_2(ring->ring_size); in uvd_v1_0_start()377 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v1_0_start()378 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v1_0_start()
124 u32 rb_bufsz; in r600_dma_resume() local131 rb_bufsz = order_base_2(ring->ring_size / 4); in r600_dma_resume()132 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
191 u32 rb_bufsz; in cayman_dma_resume() local210 rb_bufsz = order_base_2(ring->ring_size / 4); in cayman_dma_resume()211 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
369 u32 rb_bufsz; in cik_sdma_gfx_resume() local388 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()389 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
2670 u32 rb_bufsz; in r600_cp_resume() local2680 rb_bufsz = order_base_2(ring->ring_size / 8); in r600_cp_resume()2681 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in r600_cp_resume()2732 u32 rb_bufsz; in r600_ring_init() local2736 rb_bufsz = order_base_2(ring_size / 8); in r600_ring_init()2737 ring_size = (1 << (rb_bufsz + 1)) * 4; in r600_ring_init()3375 u32 rb_bufsz; in r600_ih_ring_init() local3378 rb_bufsz = order_base_2(ring_size / 4); in r600_ih_ring_init()3379 ring_size = (1 << rb_bufsz) * 4; in r600_ih_ring_init()3581 int rb_bufsz; in r600_irq_init() local[all …]
3646 u32 rb_bufsz; in si_cp_resume() local3663 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()3664 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()3694 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()3695 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()3718 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()3719 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()5994 int rb_bufsz; in si_irq_init() local6025 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in si_irq_init()6029 (rb_bufsz << 1)); in si_irq_init()
1112 unsigned rb_bufsz; in r100_cp_init() local1134 rb_bufsz = order_base_2(ring_size / 8); in r100_cp_init()1135 ring_size = (1 << (rb_bufsz + 1)) * 4; in r100_cp_init()1168 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | in r100_cp_init()
4444 u32 rb_bufsz; in cik_cp_gfx_resume() local4463 rb_bufsz = order_base_2(ring->ring_size / 8); in cik_cp_gfx_resume()4464 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in cik_cp_gfx_resume()7362 int rb_bufsz; in cik_irq_init() local7393 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in cik_irq_init()7397 (rb_bufsz << 1)); in cik_irq_init()
3108 u32 rb_bufsz; in evergreen_cp_resume() local3124 rb_bufsz = order_base_2(ring->ring_size / 8); in evergreen_cp_resume()3125 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in evergreen_cp_resume()