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/linux-4.1.27/sound/soc/ux500/
Dux500_msp_i2s.c144 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
172 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
209 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; in configure_protocol()
211 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
212 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; in configure_protocol()
214 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
228 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
229 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
261 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
267 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
[all …]
/linux-4.1.27/drivers/media/usb/cpia2/
Dcpia2_core.c251 cmd.buffer.registers[0].index = CPIA2_VC_ST_CTRL; in cpia2_do_command()
252 cmd.buffer.registers[0].value = CPIA2_VC_ST_CTRL_SRC_VC | in cpia2_do_command()
254 cmd.buffer.registers[1].index = CPIA2_VC_ST_CTRL; in cpia2_do_command()
255 cmd.buffer.registers[1].value = CPIA2_VC_ST_CTRL_SRC_VC | in cpia2_do_command()
264 cmd.buffer.registers[0].index = in cpia2_do_command()
266 cmd.buffer.registers[1].index = in cpia2_do_command()
268 cmd.buffer.registers[0].value = CPIA2_SYSTEM_CONTROL_CLEAR_ERR; in cpia2_do_command()
269 cmd.buffer.registers[1].value = in cpia2_do_command()
376 cmd.buffer.registers[0].index = CPIA2_VC_VC_TARGET_KB; in cpia2_do_command()
377 cmd.buffer.registers[0].value = param; in cpia2_do_command()
[all …]
Dcpia2_usb.c546 u8 request, u8 * registers, u16 start, size_t size) in write_packet() argument
548 if (!registers || size <= 0) in write_packet()
557 registers, /* buffer */ in write_packet()
568 u8 request, u8 * registers, u16 start, size_t size) in read_packet() argument
570 if (!registers || size <= 0) in read_packet()
579 registers, /* buffer */ in read_packet()
590 void *registers, in cpia2_usb_transfer_cmd() argument
601 if (!registers) { in cpia2_usb_transfer_cmd()
607 err = read_packet(udev, request, (u8 *)registers, start, count); in cpia2_usb_transfer_cmd()
611 err =write_packet(udev, request, (u8 *)registers, start, count); in cpia2_usb_transfer_cmd()
[all …]
/linux-4.1.27/drivers/media/radio/si470x/
Dradio-si470x-common.c200 radio->registers[SYSCONFIG2] &= ~SYSCONFIG2_BAND; in si470x_set_band()
201 radio->registers[SYSCONFIG2] |= radio->band << 6; in si470x_set_band()
215 radio->registers[CHANNEL] &= ~CHANNEL_CHAN; in si470x_set_chan()
216 radio->registers[CHANNEL] |= CHANNEL_TUNE | chan; in si470x_set_chan()
228 if ((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0) in si470x_set_chan()
235 radio->registers[CHANNEL] &= ~CHANNEL_TUNE; in si470x_set_chan()
248 switch ((radio->registers[SYSCONFIG2] & SYSCONFIG2_SPACE) >> 4) { in si470x_get_step()
271 chan = radio->registers[READCHAN] & READCHAN_READCHAN; in si470x_get_freq()
332 radio->registers[POWERCFG] |= POWERCFG_SEEK; in si470x_set_seek()
334 radio->registers[POWERCFG] &= ~POWERCFG_SKMODE; in si470x_set_seek()
[all …]
Dradio-si470x-i2c.c112 radio->registers[regnr] = __be16_to_cpu(buf[READ_INDEX(regnr)]); in si470x_get_register()
134 buf[i] = __cpu_to_be16(radio->registers[WRITE_INDEX(i)]); in si470x_set_register()
168 radio->registers[i] = __be16_to_cpu(buf[READ_INDEX(i)]); in si470x_get_all_registers()
197 radio->registers[SYSCONFIG1] |= SYSCONFIG1_RDSIEN; in si470x_fops_open()
198 radio->registers[SYSCONFIG1] |= SYSCONFIG1_STCIEN; in si470x_fops_open()
199 radio->registers[SYSCONFIG1] &= ~SYSCONFIG1_GPIO2; in si470x_fops_open()
200 radio->registers[SYSCONFIG1] |= 0x1 << 2; in si470x_fops_open()
270 if (radio->registers[STATUSRSSI] & STATUSRSSI_STC) in si470x_i2c_interrupt()
274 if ((radio->registers[SYSCONFIG1] & SYSCONFIG1_RDS) == 0) in si470x_i2c_interrupt()
285 if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSR) == 0) in si470x_i2c_interrupt()
[all …]
Dradio-si470x-usb.c266 radio->registers[regnr] = get_unaligned_be16(&radio->usb_buf[1]); in si470x_get_register()
280 put_unaligned_be16(radio->registers[regnr], &radio->usb_buf[1]); in si470x_set_register()
307 radio->registers[regnr] = get_unaligned_be16( in si470x_get_all_registers()
401 radio->registers[STATUSRSSI] = in si470x_int_in_callback()
404 if (radio->registers[STATUSRSSI] & STATUSRSSI_STC) in si470x_int_in_callback()
407 if ((radio->registers[SYSCONFIG1] & SYSCONFIG1_RDS)) { in si470x_int_in_callback()
410 radio->registers[STATUSRSSI + regnr] = in si470x_int_in_callback()
414 if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSR) == 0) { in si470x_int_in_callback()
418 if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSS) == 0) { in si470x_int_in_callback()
425 bler = (radio->registers[STATUSRSSI] & in si470x_int_in_callback()
[all …]
/linux-4.1.27/arch/mn10300/mm/
Dmisalignment.c43 static int misalignment_addr(unsigned long *registers, unsigned long sp,
49 static int misalignment_reg(unsigned long *registers, unsigned params,
321 unsigned long *registers = (unsigned long *) regs; in misalignment() local
495 if (!misalignment_addr(registers, sp, in misalignment()
500 if (!misalignment_reg(registers, pop->params[1], opcode, disp, in misalignment()
516 if (!misalignment_reg(registers, pop->params[0], opcode, disp, in misalignment()
520 if (!misalignment_addr(registers, sp, in misalignment()
548 static int misalignment_addr(unsigned long *registers, unsigned long sp, in misalignment_addr() argument
567 postinc = &registers[Dreg_index[opcode & 0x03]]; in misalignment_addr()
571 postinc = &registers[Dreg_index[opcode >> 2 & 0x03]]; in misalignment_addr()
[all …]
DKconfig.cache62 bool "Use the cache tag registers directly"
66 bool "Flush areas by way of automatic purge registers (AM34 only)"
113 icache using the cache tag registers to make breakpoints work.
122 icache using automatic purge registers to make breakpoints work.
131 tag registers to make breakpoints work.
140 purge registers to make breakpoints work.
/linux-4.1.27/Documentation/devicetree/bindings/usb/
Dsamsung-usbphy.txt15 - reg : base physical address of the phy registers and length of memory mapped
23 - reg : base physical address of the phy registers and length of memory mapped
37 - reg : base physical address of PHY_CONTROL registers.
39 registers that the SoC has. For example, the size will be
42 and, '0x8' in case we have two PHY_CONTROL registers (e.g.
43 USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
60 /* USB device and host PHY_CONTROL registers */
76 - reg : base physical address of the phy registers and length of memory mapped
93 - reg : base physical address of PHY_CONTROL registers.
95 registers that the SoC has. For example, the size will be
[all …]
Dnvidia,tegra20-usb-phy.txt10 - reg : Defines the following set of registers, in the order listed:
13 - The register set of the PHY containing the UTMI pad control registers.
18 - reg: The clock needed to access the PHY's own registers. This is the
22 - utmi-pads: The clock needed to access the UTMI pad control registers.
31 registers. Required even if phy_type == ulpi.
59 registers are accessed through the APB_MISC base address instead of
68 - nvidia,has-utmi-pad-registers : boolean indicates whether this controller
69 contains the UTMI pad control registers common to all USB controllers.
Dusb-ehci.txt6 register set for the device. Optional platform-dependent registers
8 definition of standard EHCI registers.
12 - big-endian-regs : boolean, set this for hcds with big-endian registers
Dusbmisc-imx.txt1 * Freescale i.MX non-core registers
9 - reg: Should contain registers location and length
/linux-4.1.27/Documentation/devicetree/bindings/powerpc/nintendo/
Dwii.txt31 - reg : should contain the VI registers location and length
42 - reg : should contain the PI registers location and length
64 - reg : should contain the DSP registers location and length
76 - reg : should contain the SI registers location and length
87 - reg : should contain the AI registers location and length
97 - reg : should contain the EXI registers location and length
107 - reg : should contain the OHCI registers location and length
117 - reg : should contain the EHCI registers location and length
127 - reg : should contain the SDHCI registers location and length
136 - reg : should contain the IPC registers location and length
[all …]
Dgamecube.txt22 - reg : should contain the VI registers location and length
33 - reg : should contain the PI registers location and length
53 - reg : should contain the DSP registers location and length
74 - reg : should contain the DI registers location and length
85 - reg : should contain the AI registers location and length
97 - reg : should contain the SI registers location and length
107 - reg : should contain the EXI registers location and length
/linux-4.1.27/drivers/char/agp/
Damd-k7-agp.c31 volatile u8 __iomem *registers; member
214 if (!amd_irongate_private.registers) { in amd_irongate_configure()
217 amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096); in amd_irongate_configure()
218 if (!amd_irongate_private.registers) in amd_irongate_configure()
223 writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE); in amd_irongate_configure()
224 readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */ in amd_irongate_configure()
233 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
235 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
236 readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */ in amd_irongate_configure()
244 writel(1, amd_irongate_private.registers+AMD_TLBFLUSH); in amd_irongate_configure()
[all …]
Dsworks-agp.c38 volatile u8 __iomem *registers; member
239 writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH); in serverworks_tlbflush()
241 while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) { in serverworks_tlbflush()
250 writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH); in serverworks_tlbflush()
252 while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) { in serverworks_tlbflush()
274 serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096); in serverworks_configure()
275 if (!serverworks_private.registers) { in serverworks_configure()
280 writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE); in serverworks_configure()
281 readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */ in serverworks_configure()
283 writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE); in serverworks_configure()
[all …]
Dintel-gtt.c65 u8 __iomem *registers; member
185 intel_private.registers = ioremap(reg_addr, KB(64)); in i810_setup()
186 if (!intel_private.registers) in i810_setup()
190 intel_private.registers+I810_PGETBL_CTL); in i810_setup()
194 if ((readl(intel_private.registers+I810_DRAM_CTL) in i810_setup()
206 writel(0, intel_private.registers+I810_PGETBL_CTL); in i810_cleanup()
370 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); in intel_gtt_stolen_size()
443 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); in i965_adjust_pgetbl_size()
445 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); in i965_adjust_pgetbl_size()
448 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); in i965_adjust_pgetbl_size()
[all …]
Dati-agp.c50 volatile u8 __iomem *registers; member
172 writel(1, ati_generic_private.registers+ATI_GART_CACHE_CNTRL); in ati_tlbflush()
173 readl(ati_generic_private.registers+ATI_GART_CACHE_CNTRL); /* PCI Posting. */ in ati_tlbflush()
193 iounmap((volatile u8 __iomem *)ati_generic_private.registers); in ati_cleanup()
204 ati_generic_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096); in ati_configure()
206 if (!ati_generic_private.registers) in ati_configure()
220 writel(0x60000, ati_generic_private.registers+ATI_GART_FEATURE_ID); in ati_configure()
221 readl(ati_generic_private.registers+ATI_GART_FEATURE_ID); /* PCI Posting.*/ in ati_configure()
228 writel(agp_bridge->gatt_bus_addr, ati_generic_private.registers+ATI_GART_BASE); in ati_configure()
229 readl(ati_generic_private.registers+ATI_GART_BASE); /* PCI Posting. */ in ati_configure()
/linux-4.1.27/Documentation/devicetree/bindings/arm/
Dcoherency-fabric.txt18 - reg: Should contain coherency fabric registers location and
22 fabric registers, second pair for the per-CPU fabric registers.
25 for the per-CPU fabric registers.
28 for the per-CPU fabric registers.
Dversatile-sysreg.txt1 ARM Versatile system registers
4 This is a system control registers block, providing multiple low level
10 - reg : physical base address and the size of the registers window
Dmarvell,berlin.txt46 individual registers dealing with pinmux, padmux, clock, reset, and secondary
47 CPU boot address. Unfortunately, the individual registers are spread among the
48 chip control registers, so there should be a single DT node only providing the
58 BG2Q: chip control register set and cpu pll registers
63 individual registers dealing with pinmux, padmux, and reset.
74 As clock related registers are spread among the chip control registers, the
94 Pin control registers are part of both register sets, chip control and system
111 A reset controller is part of the chip control registers set. The chip control
Dmarvell,dove.txt9 * Global Configuration registers
11 Global Configuration registers of Dove SoC are shared by a syscon node.
15 - reg: base address and size of the Global Configuration registers.
Datmel-at91.txt44 - reg: Should contain registers location and length
50 - reg: Should contain registers location and length
59 - reg: Should contain registers location and length
91 - reg: Should contain registers location and length
105 - reg: Should contain registers location and length
119 - reg: Should contain registers location and length
152 - reg: Should contain registers location and length
Dccn.txt9 - reg: (standard registers property) physical address and size
10 (16MB) of the configuration registers block
Dfw-cfg.txt11 registers; their location is communicated to the guest's UEFI firmware in the
37 The presence of the registers can be verified by selecting the "signature" blob
42 data registers) is expected to be versioned, and/or described by feature bits.
48 The guest kernel is not expected to use these registers (although it is
59 * Further registers may be appended to the region in case of future interface
Darch_timer.txt30 - arm,cpu-registers-not-fw-configured : Firmware does not initialize
31 any of the generic timer CPU registers, which contain their
53 only when firmware has not configured the MMIO CNTFRQ registers.
58 the CPU can address a frame's registers.
Dvexpress-sysreg.txt1 ARM Versatile Express system registers
4 This is a system control registers block, providing multiple low level
10 - reg : physical base address and the size of the registers window
21 Control registers providing pseudo-GPIO lines must be represented
Darm-boards22 - regs: the location and size of the core module registers, one
26 system controller node pointing to the control registers,
33 - regs: the location and size of the system controller registers,
125 system controller node pointing to the control registers,
134 - regs: the location and size of the system controller registers,
Dcci.txt11 space and multiple sets of interface control registers, one per slave
42 address of CCI control registers common to all
86 registers.
101 secure acces to CCI registers
109 registers.
223 This CCI node corresponds to a CCI component whose control registers sits
Dvexpress-scc.txt8 In some cases its registers are also mapped in normal address space
24 registers window
Dfsl.txt102 configuration and status registers for the chip. Such as getting PEX port
106 - reg: should contain base address and length of SCFG memory-mapped registers
120 - reg : should contain base address and length of DCFG memory-mapped registers
/linux-4.1.27/Documentation/metag/
Dkernel-ABI.txt8 (*) Outline of registers
9 (*) Userland registers
10 (*) Kernel registers
19 The main Meta core registers are arranged in units:
34 GP registers form part of the main context.
36 Extended context registers (EXT) may not be present on all hardware threads and
40 Global registers are shared between threads and are privilege protected.
43 registers and the fields and bits they contain. See the TRMs for further details
44 about special registers.
46 Several special registers are preserved in the main context, these are the
[all …]
/linux-4.1.27/Documentation/sh/
Dregister-banks.txt14 In the case of this type of banking, banked registers are mapped directly to
16 can still be used to reference the banked registers (as r0_bank ... r7_bank)
18 in mind when writing code that utilizes these banked registers, for obvious
20 be used rather effectively as scratch registers by the kernel.
22 Presently the kernel uses several of these registers.
25 registers when doing exception handling).
/linux-4.1.27/Documentation/video4linux/
Dcpia2_overview.txt17 The cameras appear externally as three sets of registers. Setting register
24 registers that control housekeeping functions such as powering up the video
25 processor. The video processor is the VP block. These registers control
26 how the video from the sensor is processed. Examples are timing registers,
31 of these registers and the possible values for most of them.
33 One or more registers can be set or read by sending a usb control message to
35 of contiguous registers. Random mode reads or writes random registers with
/linux-4.1.27/Documentation/devicetree/bindings/interrupt-controller/
Dmarvell,armada-370-xp-mpic.txt12 - reg: Should contain PMIC registers location and length. First pair
13 for the main interrupt registers, second pair for the per-CPU
14 interrupt registers. For this last pair, to be compliant with SMP
15 support, the "virtual" must be use (For the record, these registers
16 automatically map to the interrupt controller registers of the
Dti,keystone-irq.txt6 analyzing SRCCx bits in IPCARx registers. This is one of the component
12 access device control registers and the offset inside
13 device control registers range.
Dmarvell,orion-intc.txt7 - reg: base address(es) of interrupt registers starting with CAUSE register
12 registers, i.e.
30 - reg: base address of bridge interrupt registers starting with CAUSE register
Ddigicolor-ic.txt7 registers (IC) area
11 - syscon: A phandle to the syscon node describing UC registers
Dst,sti-irq-syscfg.txt5 and PL310 L2 Cache IRQs are controlled using System Configuration registers.
14 - st,syscfg : Phandle to Cortex-A9 IRQ system config registers
/linux-4.1.27/drivers/gpio/
Dgpio-74x164.c26 u32 registers; member
41 msg_buf = kzalloc(chip->registers * sizeof(struct spi_transfer), in __gen_74x164_write_config()
56 for (i = chip->registers - 1; i >= 0; i--) { in __gen_74x164_write_config()
134 &chip->registers)) { in gen_74x164_probe()
140 chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers; in gen_74x164_probe()
141 chip->buffer = devm_kzalloc(&spi->dev, chip->registers, GFP_KERNEL); in gen_74x164_probe()
/linux-4.1.27/Documentation/devicetree/bindings/mfd/
Dsyscon.txt4 of miscellaneous registers. The registers are not cohesive enough to
9 OS driver) to determine the location of the registers, and access the
10 registers directly.
Dqcom,tcsr.txt3 Qualcomm devices have a set of registers that provide various control and status
5 registers via syscon.
16 - reg: Address range for TCSR registers
Dmfd.txt14 - A range of memory registers containing "miscellaneous system registers" also
24 probe registers to figure out what child devices exist etc, this should not
Dti-keystone-devctrl.txt3 The Keystone II devices have a set of registers that are used to control
12 registers space.
/linux-4.1.27/Documentation/devicetree/bindings/pci/
Dmvebu-pci.txt15 - ranges: ranges describing the MMIO registers to control the PCIe
21 The ranges describing the MMIO registers have the following layout:
28 registers of this PCIe interface, from the base of the internal
29 registers.
32 registers area. This range entry translates the '0x82000000 0 r' PCI
62 - assigned-addresses: reference to the MMIO registers used to control
97 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
98 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
99 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
100 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
D83xx-512x-pci.txt7 The first is for the internal pci bridge registers
8 The second is for the pci config space access registers
36 reg = <0xe0008500 0x100 /* internal registers */
37 0xe0008300 0x8>; /* config space access registers */
Dxgene-pci.txt7 registers. Must contain an entry for each entry in the reg-names
10 "csr": controller configuration registers.
11 "cfg": pcie configuration space registers.
37 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
Dnvidia,tegra20-pcie.txt10 registers. Must contain an entry for each entry in the reg-names property.
12 "pads": PADS registers
13 "afi": AFI registers
35 port registers, which are referenced by the assigned-addresses property of
114 - assigned-addresses: Address and size of the port configuration registers
132 reg = <0x80003000 0x00000800 /* PADS registers */
133 0x80003800 0x00000200 /* AFI registers */
148 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
149 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
Dlayerscape-pci.txt16 This is used to get SCFG PEXN registers
22 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
Dti-pci.txt6 - reg-names : The first entry must be "ti-conf" for the TI specific registers
8 registers
Dpci-rcar-gen2.txt12 the operational registers for the OHCI/EHCI controllers and the
13 second is for the bridge configuration and control registers.
/linux-4.1.27/Documentation/devicetree/bindings/powerpc/4xx/
Dppc440spe-adma.txt16 - reg : <registers mapping>
17 - dcr-reg : <DCR registers range>
35 - reg : <registers mapping>
36 - dcr-reg : <DCR registers range>
66 - reg : <registers mapping>
85 - dcr-reg : <DCR registers range>
Dakebono.txt21 - reg : should contain the SDHCI registers location and length.
32 - reg : should contain the AHCI registers location and length.
44 - reg : should contain the FPGA registers location and length.
Demac.txt22 - reg : <registers mapping>
49 - mdio-device : 1 cell, required iff using shared MDIO registers
123 - dcr-reg : < DCR registers range >
135 - reg : <registers mapping>
144 - reg : <registers mapping>
Dcpm.txt11 registers. Some have the CPM registers
/linux-4.1.27/Documentation/ABI/testing/
Dsysfs-class-mei21 Description: Display fw status registers content
24 registers for BIOS and OS to monitor fw health.
27 state, error codes, and others. The way the registers
29 Also number of registers varies between 1 and 6
Dsysfs-driver-tegra-fuse8 as decoded from the fuse registers. Bits order/assignment
9 exactly matches the HW registers, including any unused bits.
Dsysfs-bus-iio-light-lm3533-als33 registers (boundaryY_{low,high}) and define the five light
60 These values correspond to the ALS-mapper target registers for
/linux-4.1.27/Documentation/mn10300/
DABI.txt13 separate stack pointer registers for userspace and the kernel.
21 passed in the D0 and D1 registers respectively; all other arguments are passed
25 registers and the stack. If the first argument is a 64-bit value, it will be
31 registers or word-sized stack slots.
85 The values in certain registers may be clobbered by the callee, and other
91 All other non-supervisor-only registers are clobberable (such as MDR, MCRL,
99 Certain ordinary registers may carry special usage for the compiler:
148 All other registers are saved. The layout is a consequence of the way the MOVM
149 instruction stores registers onto the stack.
/linux-4.1.27/drivers/usb/storage/
Dshuttle_usbat.c521 unsigned char *registers, in usbat_hp8200e_rw_block_test() argument
598 data[j<<1] = registers[j]; in usbat_hp8200e_rw_block_test()
685 unsigned char *registers, in usbat_multiple_write() argument
716 data[i<<1] = registers[i]; in usbat_multiple_write()
1061 unsigned char registers[3] = { in usbat_flash_get_sector_count() local
1079 rc = usbat_multiple_write(us, registers, command, 3); in usbat_flash_get_sector_count()
1119 unsigned char registers[7] = { in usbat_flash_read_data() local
1175 result = usbat_multiple_write(us, registers, command, 7); in usbat_flash_read_data()
1210 unsigned char registers[7] = { in usbat_flash_write_data() local
1270 result = usbat_multiple_write(us, registers, command, 7); in usbat_flash_write_data()
[all …]
/linux-4.1.27/drivers/gpu/drm/tilcdc/
Dtilcdc_drv.c428 } registers[] = { variable
467 for (i = 0; i < ARRAY_SIZE(registers); i++) in tilcdc_regs_show()
468 if (priv->rev >= registers[i].rev) in tilcdc_regs_show()
469 seq_printf(m, "%s:\t %08x\n", registers[i].name, in tilcdc_regs_show()
470 tilcdc_read(dev, registers[i].reg)); in tilcdc_regs_show()
583 for (i = 0; i < ARRAY_SIZE(registers); i++) in tilcdc_pm_suspend()
584 if (registers[i].save && (priv->rev >= registers[i].rev)) in tilcdc_pm_suspend()
585 priv->saved_register[n++] = tilcdc_read(ddev, registers[i].reg); in tilcdc_pm_suspend()
597 for (i = 0; i < ARRAY_SIZE(registers); i++) in tilcdc_pm_resume()
598 if (registers[i].save && (priv->rev >= registers[i].rev)) in tilcdc_pm_resume()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/gpio/
Dgpio-74x164.txt11 - registers-number: Number of daisy-chained shift registers
20 registers-number = <4>;
Dgpio-dsp-keystone.txt19 access device state control registers and the offset of device's specific
20 registers within device state control registers range.
Dgpio-clps711x.txt5 - reg: Physical base GPIO controller registers location and length.
6 There should be two registers, first is DATA register, the second
Dgpio-mvebu.txt14 for which two entries are expected: one for the general registers,
15 one for the per-cpu registers.
Dspear_spics.txt4 Cell spi controller through its system registers, which otherwise remains under
11 provides another interface through system registers through which software can
/linux-4.1.27/Documentation/devicetree/bindings/spmi/
Dqcom,spmi-pmic-arb.txt19 "core" - core registers
20 "intr" - interrupt controller registers
21 "cnfg" - configuration registers
23 "chnls" - tx-channel per virtual slave registers.
24 "obsrvr" - rx-channel (called observer) per virtual slave registers.
/linux-4.1.27/Documentation/devicetree/bindings/phy/
Ddm816x-phy.txt7 - reg-names : name for the phy registers
10 - syscon: phandle for the syscon node to access misc registers
12 - syscon: phandle for the syscon node to access misc registers
Dsamsung-phy.txt24 control pmu registers for power isolation.
37 - reg : a list of registers used by phy driver
38 - first and obligatory is the location of phy modules registers
39 - samsung,sysreg-phandle - handle to syscon used to control the system registers
40 - samsung,pmureg-phandle - handle to syscon used to control PMU registers
149 control pmu registers for power isolation.
/linux-4.1.27/Documentation/devicetree/bindings/powerpc/fsl/
Dmpic-msgr.txt12 the MPIC containing the message registers.
25 - mpic-msgr-receive-mask: Specifies what registers in the containing block
29 be <u32>. If not present, then all of the message registers in the block
50 // Message registers 0 and 2 in this block can receive interrupts on
59 // Message registers 0 and 2 in this block can receive interrupts on
Dmpic.txt26 offset and length of the device's registers within the
53 configuration registers to a sane state-- masked or
77 in the global feature registers. If specified, this field will
112 MPIC a block of registers referred to as
114 Each source has 32-bytes of registers
165 * registers at 0x5_0560.
167 * The interrupt source configuration registers begin
174 * The interrupt source configuration registers begin
175 * at 0x5_0000, and so the i2c vector/priority registers
Dmcm.txt25 registers.
38 and error reporting registers exist, this is the second 4k (0x1000)
54 registers.
Decm.txt25 registers.
38 and error reporting registers exist, this is the second 4k (0x1000)
54 registers.
Ddcsr.txt98 offset and length of the DCSR space registers of the device
127 offset and length of the DCSR space registers of the device
133 control and status registers.
164 offset and length of the DCSR space registers of the device
189 offset and length of the DCSR space registers of the device
226 offset and length of the DCSR space registers of the device
254 offset and length of the DCSR space registers of the device
285 offset and length of the DCSR space registers of the device
314 offset and length of the DCSR space registers of the device
344 offset and length of the DCSR space registers of the device
[all …]
Dpamu.txt32 A standard property. It represents the CCSR registers of
39 Snoop ID Port Mapping registers, which are part of the
42 functions. Certain bits from these registers should be
56 PAMU controller's configuration registers. The size should
89 the registers where the LIODN is to be set. The second is
Dboard.txt22 This is the memory-mapped registers for on board FPGA.
43 Some BCSR registers act as simple GPIO controllers, each such
96 - reg: should describe CPLD registers
Dcpus.txt28 Snoop ID Port Mapping registers, which are part of the CoreNet
31 these registers should be set if the coresponding CPU should be
Dccf.txt17 fsl,corenet-cf - Used to represent the common registers
25 A standard property. Represents the CCF registers.
Dfman.txt68 following configuration registers:
69 - BMI configuration registers.
70 - QMI configuration registers.
71 - DMA configuration registers.
72 - FPM configuration registers.
73 - FMan controller configuration registers.
181 memory region is used for what are called common registers.
190 configuration registers.
264 2. SoC registers:
Dsrio-rmu.txt22 length of the SRIO configuration registers for message units
53 length of the SRIO configuration registers for message units
83 length of the SRIO configuration registers for message units
113 length of the SRIO configuration registers for message units
/linux-4.1.27/Documentation/devicetree/bindings/c6x/
Ddscr.txt4 TI C6X SoCs contain a region of miscellaneous registers which provide various
9 more configuration registers often protected by a lock register where one or
15 the DSCR block may provide registers which are used to reset peripherals,
45 possibly multiple tuples describing registers which are write protected by
50 offset and key values of two "kick" registers used to write protect other
51 registers in DSCR. On SoCs using kick registers, the first key must be
53 the second register before other registers in the area are write-enabled.
56 MAC addresses are contained in two registers. Each element of a MAC address
/linux-4.1.27/drivers/char/xillybus/
Dxillybus_core.c164 ep->registers + fpga_msg_ctrl_reg); in xillybus_isr()
299 iowrite32(0x03, ep->registers + fpga_msg_ctrl_reg); /* Message ACK */ in xillybus_isr()
379 ep->registers + fpga_dma_bufaddr_lowaddr_reg); in xilly_get_dma_buffers()
381 ep->registers + fpga_dma_bufaddr_highaddr_reg); in xilly_get_dma_buffers()
389 ep->registers + fpga_dma_bufno_reg); in xilly_get_dma_buffers()
396 ep->registers + fpga_dma_bufno_reg); in xilly_get_dma_buffers()
620 endpoint->registers + fpga_buf_ctrl_reg); in xilly_obtain_idt()
782 channel->endpoint->registers + in xillybus_read()
867 channel->endpoint->registers + in xillybus_read()
873 channel->endpoint->registers + in xillybus_read()
[all …]
Dxillybus_of.c149 endpoint->registers = devm_ioremap_resource(dev, &res); in xilly_drv_probe()
151 if (IS_ERR(endpoint->registers)) in xilly_drv_probe()
152 return PTR_ERR(endpoint->registers); in xilly_drv_probe()
/linux-4.1.27/Documentation/parisc/
D00-INDEX5 registers
6 - current/planned usage of registers
Dregisters82 The PA-RISC architecture defines 7 registers as "shadow registers".
86 Shadow registers are the GRs 1, 8, 9, 16, 17, 24, and 25.
92 For the general registers:
96 another procedure. Some of the above registers do have special meanings
104 caller. However, it is grouped with this set of registers
110 r19-r22: these are generally regarded as temporary registers.
126 general purpose registers. r27 is the data pointer, and is
/linux-4.1.27/arch/arm/include/asm/
Dvfpmacros.h19 @ read all the working registers back into the VFP in toolkits()
36 cmp \tmp, #2 @ 32 x 64bit registers?
43 @ write all the working registers out of the VFP
60 cmp \tmp, #2 @ 32 x 64bit registers?
/linux-4.1.27/Documentation/video4linux/cx2341x/
Dfw-decoder-regs.txt1 PVR350 Video decoder registers 0x02002800 -> 0x02002B00
5 and omissions. Some registers have no obvious effect so it's hard to say what
7 sequence. Horizontal filter setup is one example, with six registers working
9 indexed colour palette is much easier to set at just two registers, but again
12 Some registers are fussy about what they are set to. Load in a bad value & the
14 is required. For registers containing size information, setting them to 0 is
15 generally a bad idea. For other control registers i.e. 2878, you'll only find
49 These six registers control the horizontal aliasing filter for the Y plane.
50 The first five registers must all be loaded before accessing the trigger
83 These six registers control the horizontal aliasing for the UV plane.
[all …]
Dfw-memory.txt7 registers, this information may not be correct and is certainly not complete, and
40 The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
41 All of these registers are 32 bits wide.
78 0xec-0xff - Nothing seems to be in these registers, 0xec-f4 are 0x00000000.
82 These registers show offsets of memory locations pertaining to each
90 These registers show offsets of memory locations pertaining to each
/linux-4.1.27/Documentation/devicetree/bindings/net/
Dkeystone-netcp.txt77 - switch subsystem registers
78 - sgmii port3/4 module registers (only for NetCP 1.4)
79 - switch module registers
80 - serdes registers (only for 10G)
83 index #0 - switch subsystem registers
84 index #1 - sgmii port3/4 module registers
85 index #2 - switch module registers
88 index #0 - switch subsystem registers
89 index #1 - switch module registers
90 index #2 - serdes registers
Dcavium-mix.txt10 bank contains the MIX registers. The second bank the corresponding
11 AGL registers. The third bank are the AGL registers shared by all
Damd-xgbe-phy.txt7 - SerDes Rx/Tx registers
8 - SerDes integration registers (1/2)
9 - SerDes integration registers (2/2)
Dmarvell-orion-net.txt11 the multiple levels is that the port registers are interleaved within a single
12 set of controller registers. Each port node describes port-specific properties.
26 - reg: address and length of the controller registers.
Dmarvell-pp2.txt8 - common controller registers
9 - LMS registers
Damd-xgbe.txt6 - MAC registers
7 - PCS registers
/linux-4.1.27/drivers/iio/adc/
Dat91_adc.c138 (st->registers->channel_base + (ch * 4))
188 struct at91_adc_reg_desc registers; member
203 struct at91_adc_reg_desc *registers; member
351 u32 status = at91_adc_readl(st, st->registers->status_register); in at91_adc_rl_interrupt()
368 at91_adc_writel(st, st->registers->trigger_register, in at91_adc_rl_interrupt()
375 at91_adc_writel(st, st->registers->trigger_register, in at91_adc_rl_interrupt()
416 u32 status = at91_adc_readl(st, st->registers->status_register); in at91_adc_9x5_interrupt()
430 at91_adc_writel(st, st->registers->trigger_register, in at91_adc_9x5_interrupt()
434 at91_adc_writel(st, st->registers->trigger_register, 0); in at91_adc_9x5_interrupt()
547 struct at91_adc_reg_desc *reg = st->registers; in at91_adc_configure_trigger()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/clock/
Dmoxa,moxart-clock.txt8 by reading registers holding multiplier and divisor information.
16 - reg : Should contain registers location and length
28 - reg : Should contain registers location and length
Dkeystone-pll.txt6 PLL is controlled by a PLL controller registers along with memory mapped
7 registers.
17 - reg - pll control0 and pll multipler registers
19 post-divider registers are applicable only for main pll clock
Dpistachio-clock.txt76 control registers. The system clock ("sys") generated by the peripheral clock
82 control registers.
102 The top-level general control block contains miscellaneous control registers and
108 control registers.
Dnvidia,tegra30-car.txt11 - reg : Should contain CAR registers location and length
20 array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
Dnvidia,tegra20-car.txt11 - reg : Should contain CAR registers location and length
20 array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
Dnvidia,tegra114-car.txt11 - reg : Should contain CAR registers location and length
20 array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
Dnvidia,tegra124-car.txt11 - reg : Should contain CAR registers location and length
22 array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
Drockchip.txt12 The gate registers form a continuos block which makes the dt node
14 one gate clock spanning all registers or they can be divided into
/linux-4.1.27/Documentation/devicetree/bindings/dma/
Dmv-xor.txt5 - reg: Should contain registers location and length (two sets)
6 the first set is the low registers, the second set the high
7 registers for the XOR engine.
Dtegra20-apbdma.txt5 - reg: Should contain DMA registers location and length. This shuld include
6 all of the per-channel registers.
Dfsl-edma.txt4 registers. channels are split into two groups, called DMAMUX0 and DMAMUX1,
12 - reg : Specifies base physical address(s) and size of the eDMA registers.
35 - big-endian: If present registers and hardware scatter/gather descriptors
Dmmp-dma.txt8 - reg: Should contain DMA registers location and length.
55 - reg: Should contain DMA registers location and length.
Dimg-mdc-dma.txt5 - reg: Must contain the base address and length of the MDC registers.
12 node which contains the DMA request to channel mapping registers.
/linux-4.1.27/arch/s390/kernel/
Dsclp.S33 stm %r6,%r15,24(%r15) # save registers
83 lm %r6,%r15,120(%r15) # restore registers
113 stm %r6,%r15,24(%r15) # save registers
131 lm %r6,%r15,120(%r15) # restore registers
145 stm %r6,%r15,24(%r15) # save registers
177 lm %r6,%r15,120(%r15) # restore registers
205 stm %r6,%r15,24(%r15) # save registers
253 lm %r6,%r15,120(%r15) # restore registers
267 stm %r6,%r15,24(%r15) # save registers
294 lm %r6,%r15,120(%r15) # restore registers
Dhead64.S22 lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
47 .Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space
55 .quad 0 # cr8: access registers translation
89 # check control registers
/linux-4.1.27/Documentation/devicetree/bindings/arm/hisilicon/
Dhisilicon.txt51 system controller,but it has some specific control registers for
53 registers located at different offset.
71 The clock registers and power registers of secondary cores are defined
/linux-4.1.27/Documentation/devicetree/bindings/arm/spear/
Dshirq.txt9 may share same set of status/mask registers spanning across different
11 registers. This makes software little complex.
15 interrupt controller shares config/control registers with other groups.
27 - reg: Base address and size of shirq registers.
/linux-4.1.27/drivers/firewire/
Dinit_ohci1394_dma.c50 void __iomem *registers; member
55 writel(data, ohci->registers + offset); in reg_write()
60 return readl(ohci->registers + offset); in reg_read()
261 ohci.registers = (void __iomem *)fix_to_virt(FIX_OHCI1394_BASE); in init_ohci1394_controller()
Dnosy.c81 __iomem char *registers; member
228 writel(data, lynx->registers + offset); in reg_write()
234 return readl(lynx->registers + offset); in reg_read()
525 iounmap(lynx->registers); in remove_card()
563 lynx->registers = ioremap_nocache(pci_resource_start(dev, 0), in add_card()
677 iounmap(lynx->registers); in add_card()
/linux-4.1.27/Documentation/devicetree/bindings/iommu/
Dnvidia,tegra20-gart.txt6 the memory controller registers and the GART aperture respectively.
12 reg = <0x7000f024 0x00000018 /* controller registers */
/linux-4.1.27/drivers/scsi/aic7xxx/aicasm/
Daicasm_symbol.c471 symlist_t registers; in symtable_dump() local
488 SLIST_INIT(&registers); in symtable_dump()
503 symlist_add(&registers, cursym, SYMLIST_SORT); in symtable_dump()
540 SLIST_FOREACH(curnode, &registers, links) { in symtable_dump()
588 regnode = symlist_search(&registers, regname); in symtable_dump()
600 regnode = symlist_search(&registers, regname); in symtable_dump()
605 while (SLIST_FIRST(&registers) != NULL) { in symtable_dump()
611 curnode = SLIST_FIRST(&registers); in symtable_dump()
612 SLIST_REMOVE_HEAD(&registers, links); in symtable_dump()
/linux-4.1.27/arch/arm/boot/dts/
Darmada-xp-mv78460.dtsi119 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
120 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
121 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
122 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
123 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
124 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
125 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
126 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
127 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
128 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
Darmada-xp-mv78260.dtsi102 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
103 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
104 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
105 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
106 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
107 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
108 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
109 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
110 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
Darmada-xp-mv78230.dtsi101 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
102 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
103 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
104 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
105 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
Dtegra20.dtsi257 reg = <0x70000014 0x10 /* Tri-state registers */
258 0x70000080 0x20 /* Mux registers */
259 0x700000a0 0x14 /* Pull-up/down registers */
260 0x70000868 0xa8>; /* Pad control registers */
553 reg = <0x7000f024 0x00000018 /* controller registers */
576 reg = <0x80003000 0x00000800 /* PADS registers */
577 0x80003800 0x00000200 /* AFI registers */
592 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
593 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
668 nvidia,has-utmi-pad-registers;
/linux-4.1.27/Documentation/devicetree/bindings/arm/freescale/
Dfsl,vf610-mscm-cpucfg.txt4 block of registers which contains CPU configuration information.
8 - reg: the register range of the MSCM CPU configuration registers
/linux-4.1.27/Documentation/devicetree/bindings/power/reset/
Dkeystone-reset.txt17 access pll controller registers and the offset to use
18 reset control registers.
21 access device state control registers and the offset
22 in order to use mux block registers for all watchdogs.
/linux-4.1.27/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,brcmstb.txt16 Further, syscon nodes that map platform-specific registers used for general
58 of certain CPU power-on registers.
67 continuation registers.
88 the general system reset registers.
/linux-4.1.27/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-mc.txt6 example below. Note that the MC registers are interleaved with the
7 GART registers, and hence must be represented as multiple ranges.
Dnvidia,tegra30-mc.txt6 example below. Note that the MC registers are interleaved with the
7 SMMU registers, and hence must be represented as multiple ranges.
Dnvidia,tegra20-emc.txt71 - nvidia,emc-registers : a 46 word array of EMC registers to be programmed
73 The order and contents of the registers are:
86 nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
96 nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
/linux-4.1.27/Documentation/devicetree/bindings/thermal/
Ddove-thermal.txt7 - reg : Address range of the thermal registers
10 three Thermal Manager registers, while the second range contains the
Dexynos-thermal.txt17 - reg : Address range of the thermal registers. For soc's which has multiple
18 instances of TMU and some registers are shared across all TMU's like
21 registers shared with the TMU instance.
35 -- 2. optional clock to access the shared registers of TMU channel
/linux-4.1.27/Documentation/devicetree/bindings/rng/
Dqcom,prng.txt6 - reg : specifies base physical address and size of the registers map
8 - clock-names : "core" clocks all registers, FIFO and circuits in PRNG IP block
Dbrcm,bcm2835.txt6 - reg : Specifies base physical address and size of the registers.
/linux-4.1.27/Documentation/hwmon/
Dsmsc47b39732 HWM Base address can be obtained from Logical Device 8, registers 0x60 (MSB)
37 The temperature information is located in the following registers:
44 The following is an example of how to read the HWM temperature registers:
57 The fan speed information is located in the following registers:
85 To program the configuration registers, the following sequence must be followed:
98 The desired configuration registers are accessed in two steps:
132 The registers of interest for identifying the SIO on the dc7100 are Device ID
Dw83627ehf7 Addresses scanned: ISA address retrieved from Super I/O registers
11 Addresses scanned: ISA address retrieved from Super I/O registers
15 Addresses scanned: ISA address retrieved from Super I/O registers
19 Addresses scanned: ISA address retrieved from Super I/O registers
23 Addresses scanned: ISA address retrieved from Super I/O registers
27 Addresses scanned: ISA address retrieved from Super I/O registers
31 Addresses scanned: ISA address retrieved from Super I/O registers
35 Addresses scanned: ISA address retrieved from Super I/O registers
158 Future driver development should bear in mind that the following registers have
159 different functions on the 627EHF and the 627DHG. Some registers also have
Dw83627hf7 Addresses scanned: ISA address retrieved from Super I/O registers
10 Addresses scanned: ISA address retrieved from Super I/O registers
13 Addresses scanned: ISA address retrieved from Super I/O registers
16 Addresses scanned: ISA address retrieved from Super I/O registers
19 Addresses scanned: ISA address retrieved from Super I/O registers
Dfam15h_power18 This driver permits reading of registers providing power information
22 calculated using different processor northbridge function registers:
Dadt741122 loses 2 inputs then). There are high- and low-limit registers for all inputs.
42 SPI, external temperature sensor and limit registers are not supported yet.
Dnct677513 Addresses scanned: ISA address retrieved from Super I/O registers
17 Addresses scanned: ISA address retrieved from Super I/O registers
21 Addresses scanned: ISA address retrieved from Super I/O registers
25 Addresses scanned: ISA address retrieved from Super I/O registers
29 Addresses scanned: ISA address retrieved from Super I/O registers
33 Addresses scanned: ISA address retrieved from Super I/O registers
/linux-4.1.27/drivers/net/wireless/ath/wil6210/
DKconfig17 bool "Use Clear-On-Read mode for ISR registers for wil6210"
21 ISR registers on wil6210 chip may operate in either
26 registers with debugfs. If COR were used, ISR would
/linux-4.1.27/arch/cris/arch-v10/kernel/
Dkgdb.c231 } registers; typedef
328 registers cris_reg;
607 registers *current_reg = &cris_reg; in write_register()
643 registers *current_reg = &cris_reg; in read_register()
755 mem2hex(remcomOutBuffer, (char *)&cris_reg, sizeof(registers)); in handle_exception()
763 hex2mem((char *)&cris_reg, &remcomInBuffer[1], sizeof(registers)); in handle_exception()
/linux-4.1.27/Documentation/devicetree/bindings/watchdog/
Dfsl-imx-wdt.txt5 - reg : Should contain WDT registers location and length
9 - big-endian: If present the watchdog device's registers are implemented
Dmtk-wdt.txt6 - reg : Specifies base physical address and size of the registers.
Dingenic,jz4740-wdt.txt5 reg: Register address and length for watchdog registers
Dmeson6-wdt.txt6 - reg : Specifies base physical address and size of the registers.
/linux-4.1.27/Documentation/devicetree/bindings/misc/
Dnvidia,tegra20-apbmisc.txt9 and length of the registers which contain revision and debug features.
11 registers indicating the strapping options.
Dfsl,qoriq-mc.txt24 defining the MC's registers:
29 -the second region is the MC control registers. This
/linux-4.1.27/drivers/thermal/ti-soc-thermal/
Domap4-thermal-data.c82 .registers = &omap4430_mpu_temp_sensor_registers,
222 .registers = &omap4460_mpu_temp_sensor_registers,
255 .registers = &omap4460_mpu_temp_sensor_registers,
Ddra752-thermal-data.c434 .registers = &dra752_mpu_temp_sensor_registers,
445 .registers = &dra752_gpu_temp_sensor_registers,
454 .registers = &dra752_core_temp_sensor_registers,
463 .registers = &dra752_dspeve_temp_sensor_registers,
472 .registers = &dra752_iva_temp_sensor_registers,
Dti-bandgap.c85 t = bgp->conf->sensors[(id)].registers; \
169 tsr = bgp->conf->sensors[id].registers; in ti_bandgap_read_temp()
219 tsr = bgp->conf->sensors[i].registers; in ti_bandgap_talert_irq_handler()
412 tsr = bgp->conf->sensors[id].registers; in ti_bandgap_unmask_interrupts()
451 tsr = bgp->conf->sensors[id].registers; in ti_bandgap_update_alert_threshold()
596 tsr = bgp->conf->sensors[id].registers; in _ti_bandgap_write_threshold()
651 tsr = bgp->conf->sensors[id].registers; in _ti_bandgap_read_threshold()
738 tsr = bgp->conf->sensors[id].registers; in ti_bandgap_read_counter()
758 tsr = bgp->conf->sensors[id].registers; in ti_bandgap_read_counter_delay()
1072 tsr = bgp->conf->sensors[id].registers; in ti_bandgap_get_trend()
[all …]
Domap5-thermal-data.c334 .registers = &omap5430_mpu_temp_sensor_registers,
345 .registers = &omap5430_gpu_temp_sensor_registers,
354 .registers = &omap5430_core_temp_sensor_registers,
/linux-4.1.27/Documentation/devicetree/bindings/mmc/
Dsdhci-pxa.txt11 the SDHCI registers.
14 one for the SDHCI registers themselves, the second one for the
15 AXI/Mbus bridge registers of the SDHCI unit, the third one for the
/linux-4.1.27/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra210-pinmux.txt6 - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7 - second entry: The PINMUX_AUX_* registers (pinmux)
83 These correspond to Tegra PINMUX_AUX_* (pinmux) registers. Any property
84 that exists in those registers may be set for the following pin names.
127 registers. Note that where one of these registers controls a single pin
148 reg = <0x0 0x700008d4 0x0 0x2a8>, /* Pad control registers */
149 <0x0 0x70003000 0x0 0x1000>; /* Mux registers */
Dnvidia,tegra124-pinmux.txt12 -- first entry - the drive strength and pad control registers.
13 -- second entry - the pinmux registers
118 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
119 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
/linux-4.1.27/Documentation/devicetree/bindings/rtc/
Darmada-380-rtc.txt10 * "rtc" for the RTC registers
11 * "rtc-soc" for the SoC related registers and among them the one
Dnvidia,tegra20-rtc.txt4 registers. The alarms and other interrupts may wake the system from low-power
12 - reg : Specifies base physical address and size of the registers.
/linux-4.1.27/arch/um/os-Linux/
DMakefile7 registers.o sigio.o signal.o start_up.o time.o tty.o \
13 main.o mem.o process.o registers.o sigio.o signal.o start_up.o time.o \
/linux-4.1.27/Documentation/ia64/
Dfsys.txt24 CPU registers.
29 state remains in the CPU registers and some kernel state may
30 be stored in bank 0 of registers r16-r31.
36 - CPU registers may contain a mixture of user-level and kernel-level
100 - all other registers may contain values passed in from user-mode
120 system call restart. Of course, all "preserved" registers also
123 o Fsyscall-handlers MUST check argument registers for containing a
133 o Fsyscall-handlers MUST NOT write to any stacked registers because
144 user-level, care needs to be taken to clear any scratch registers
159 PSR.ic, switch to bank 0 (bsw.0) and then use the shadow registers as
[all …]
DIRQ-redir.txt43 fixed SAPIC mode with hint). The XTP chipset registers are used as hints
44 for the IRQ routing. Currently in Linux XTP registers can have three
67 only to their own CPUs (as they cannot see the XTP registers on the
/linux-4.1.27/Documentation/devicetree/bindings/gpu/
Dnvidia,tegra20-host1x.txt5 - reg: Physical base address and length of the controller's registers.
26 - reg: Physical base address and length of the controller's registers.
39 - reg: Physical base address and length of the controller's registers.
52 - reg: Physical base address and length of the controller's registers.
65 - reg: Physical base address and length of the controller's registers.
78 - reg: Physical base address and length of the controller's registers.
91 - reg: Physical base address and length of the controller's registers.
109 - reg: Physical base address and length of the controller's registers.
137 - reg: Physical base address and length of the controller's registers.
163 - reg: Physical base address and length of the controller's registers.
[all …]
Dst,stih4xx.txt6 - reg: Physical base address of the IP registers and length of memory mapped region.
14 - reg: Physical base address of the IP registers and length of memory mapped region.
32 - reg: Physical base address of the IP registers and length of memory mapped region.
48 - reg: Physical base address of the IP registers and length of memory mapped region.
61 - reg: Physical base address of the IP registers and length of memory mapped region.
77 - reg: Physical base address of the IP registers and length of memory mapped region.
90 - reg: Physical base address of the IP registers and length of memory mapped region.
106 - reg: Physical base address of the IP registers and length of memory mapped region.
/linux-4.1.27/Documentation/devicetree/bindings/crypto/
Datmel-crypto.txt9 - reg: Should contain AES registers location and length.
29 - reg: Should contain TDES registers location and length.
52 - reg: Should contain SHA registers location and length.
Dfsl-sec4.txt25 2. Job Rings (HW interface between cores & SEC 4 registers).
48 configuration registers for the SEC 4 block. It
82 address and length of the SEC4 configuration registers.
83 registers
144 the parent physical address and the length the JR registers.
217 the SEC4 registers.
255 1. The location of the RTIC memory address & length registers.
303 registers.
365 address and length of the SNVS LP configuration registers.
Dfsl-sec6.txt15 configuration registers for the SEC 6 block.
48 address and length of the SEC 6 configuration registers.
90 the parent physical address and the length the JR registers.
/linux-4.1.27/Documentation/devicetree/bindings/media/
Dti,omap3isp.txt11 reg : the two registers sets (physical address and length) for the
12 ISP. The first set contains the core ISP registers up to
14 CSI PHYs and receivers registers.
/linux-4.1.27/Documentation/devicetree/bindings/i2c/
Di2c-davinci.txt14 registers. PFUNC registers allow to switch I2C pins to function as
/linux-4.1.27/arch/unicore32/kernel/
Dsleep.S22 @ get coprocessor registers
53 stm.w (r16 - r27, lr), [sp-] @ save registers on stack
54 stm.w (r4 - r15), [sp-] @ save registers on stack
201 ldm.w (r4 - r15), [sp]+ @ restore registers from stack
Dhibernate_asm.S26 @ restore registers from swsusp_arch_regs_cpu0
96 @ - save registers in swsusp_arch_regs_cpu0
/linux-4.1.27/arch/frv/kernel/
Dhead-uc-fr451.S39 # set the protection map with the I/DAMPR registers
58 # set the I/O region protection registers for FR401/3/5
67 # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
68 # - start with the highest numbered registers
Dhead-uc-fr401.S39 # describe the position and layout of the SDRAM controller registers
79 # rearrange the bus controller registers
233 # set the protection map with the I/DAMPR registers
245 # set the I/O region protection registers for FR401/3/5
252 # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
253 # - start with the highest numbered registers
Dhead-uc-fr555.S38 # describe the position and layout of the SDRAM controller registers
70 # rearrange the bus controller registers
217 # set the protection map with the I/DAMPR registers
231 # set the I/O region protection registers for FR555
240 # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
241 # - start with the highest numbered registers
/linux-4.1.27/Documentation/devicetree/bindings/bus/
Dimx-weim.txt51 node's "reg" property. The number of registers depends
54 registers: CSxU, CSxL.
56 there are three registers: CSCRxU, CSCRxL, CSCRxA.
59 there are six registers: CSxGCR1, CSxGCR2, CSxRCR1,
Dmvebu-mbus.txt29 registers that control the MBus, which is typically contained
250 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
251 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
252 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
253 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
254 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
/linux-4.1.27/drivers/gpu/drm/msm/adreno/
Dadreno_gpu.c237 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { in adreno_show()
238 uint32_t start = adreno_gpu->registers[i]; in adreno_show()
239 uint32_t end = adreno_gpu->registers[i+1]; in adreno_show()
271 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { in adreno_dump()
272 uint32_t start = adreno_gpu->registers[i]; in adreno_dump()
273 uint32_t end = adreno_gpu->registers[i+1]; in adreno_dump()
/linux-4.1.27/Documentation/devicetree/bindings/sound/
Dbrcm,bcm2835-i2s.txt6 * The first entry should cover the PCM registers
7 * The second entry should cover the PCM clock registers
Dfsl,esai.txt25 "core" The core clock used to access registers
38 duplicated from Transmition related registers.
42 will be in use for all the device registers.
Dnvidia,tegra20-das.txt5 - reg : Should contain DAS registers location and length
/linux-4.1.27/Documentation/devicetree/bindings/pwm/
Dimg-pwm.txt5 - reg: Should contain physical base address and length of pwm registers.
14 syscon node which contains PWM control registers.
Dlpc32xx-pwm.txt5 - reg: physical base address and length of the controller's registers
Dpwm-fsl-ftm.txt20 - reg: Physical base address and length of the controller's registers
34 - big-endian: Boolean property, required if the FTM PWM registers use a big-
/linux-4.1.27/arch/powerpc/platforms/52xx/
Dlite5200_sleep.S34 registers: label
62 lis r4, registers@h
63 ori r4, r4, registers@l
338 lis r4, registers@h
339 ori r4, r4, registers@l
/linux-4.1.27/drivers/scsi/
Dscript_asm.pl104 %registers = (
124 %registers = (
169 $register = join ('|', keys %registers);
184 %symbol_values = (%registers) ; # Traditional symbol table
600 ($registers{$dst_reg} << 16);
603 ($registers{$src_reg} << 16);
606 ($registers{$dst_reg} << 16);
/linux-4.1.27/Documentation/devicetree/bindings/mips/cavium/
Dcib.txt11 registers of the CIB block
36 * 1) Bit number in the CIB* registers
/linux-4.1.27/arch/powerpc/kernel/
Drtas_pci.c194 struct resource registers; in python_countermeasures() local
198 if (of_address_to_resource(dev, 0, &registers)) { in python_countermeasures()
204 chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000); in python_countermeasures()
/linux-4.1.27/Documentation/frv/
Dkernel-ABI.txt6 number of the registers are used for special purposed, and the ABI is not
11 registers, thus requiring at least one general purpose register to be
31 When a system call is made, the following registers are effective:
53 Normal kernel mode. There are many additional control registers
76 All kernel mode registers may be accessed, plus a few extra debugging
77 specific registers.
113 Certain registers are also used or modified across function calls:
141 exception frame. Almost all the global registers from kernel-mode
/linux-4.1.27/Documentation/devicetree/bindings/reset/
Dst,sti-picophyreset.txt6 the STi family SoC system configuration registers.
10 registers and after an assert/deassert sequence the hardware's previous state
Dst,sti-softreset.txt7 registers.
11 registers and after an assert/deassert sequence the hardware's previous state
Dst,sti-powerdown.txt7 registers. These have been grouped together into a single reset controller
12 registers and after an assert/deassert sequence the hardware's previous state
/linux-4.1.27/Documentation/
Dsmsc_ece1099.txt18 any bit in one of the Interrupt Status registers is 1 and
34 through a series of read/write registers via the SMBus
51 device uses this serial bus to read and write registers
/linux-4.1.27/Documentation/i2c/busses/
Di2c-ocores22 distance between registers and the input clock speed.
55 .regstep = 2, /* two bytes between registers */
/linux-4.1.27/Documentation/thermal/
Dcpu-cooling-api.txt22 This interface function registers the cpufreq cooling device with the name
31 This interface function registers the cpufreq cooling device with
/linux-4.1.27/Documentation/networking/
Dfilter.txt185 M[] 16 x 32 bit wide misc registers aka "scratch memory
605 - Number of registers increase from 2 to 10:
607 The old format had two registers A and X, and a hidden frame pointer. The
608 new layout extends this to be 10 internal registers and a read-only frame
609 pointer. Since 64-bit CPUs are passing arguments to functions via registers
612 function. Natively, x86_64 passes first 6 arguments in registers, aarch64/
613 sparcv9/mips64 have 7 - 8 registers for arguments; x86_64 has 6 callee saved
614 registers, and aarch64/sparcv9/mips64 have 11 or more callee saved registers.
620 * R6 - R9 - callee saved registers that in-kernel function will preserve
623 Thus, all eBPF registers map one to one to HW registers on x86_64, aarch64,
[all …]
/linux-4.1.27/drivers/media/platform/exynos4-is/
Dfimc-lite-reg.c324 } registers[] = { in flite_hw_dump_regs() local
344 for (i = 0; i < ARRAY_SIZE(registers); i++) { in flite_hw_dump_regs()
345 u32 cfg = readl(dev->regs + registers[i].offset); in flite_hw_dump_regs()
347 registers[i].name, cfg); in flite_hw_dump_regs()
/linux-4.1.27/Documentation/misc-devices/
Dmax687522 registers. The chip then begins to operate according to the values in the
23 registers.
63 The configuration registers are at addresses 0x00 - 0x45.
/linux-4.1.27/drivers/media/i2c/
Dtvaudio.c79 int registers; /* # of registers */ member
1476 .registers = 5,
1492 .registers = 3,
1544 .registers = 11,
1556 .registers = 11,
1581 .registers = 6,
1603 .registers = 8,
1626 .registers = 1,
1639 .registers = 9,
1663 .registers = 2,
[all …]
/linux-4.1.27/drivers/hwmon/
Dina2xx.c92 int registers; member
120 .registers = INA219_REGISTERS,
129 .registers = INA226_REGISTERS,
216 for (i = 0; i < data->config->registers; i++) { in ina2xx_do_update()
/linux-4.1.27/arch/arm/kvm/
Dinterrupts_head.S21 @ Make sure VFP is enabled so we can touch the registers.
36 VFPFSTMIA \vfp_base, r6 @ Save VFP registers
42 VFPFLDMIA \vfp_base, r6 @ Load VFP registers
184 @ Load user registers
218 @ Store usr registers
235 @ Store other guest registers
262 push {r2-r12} @ Push CP15 registers
290 push {r2-r12} @ Push CP15 registers
/linux-4.1.27/arch/x86/um/os-Linux/
DMakefile6 obj-y = registers.o task_size.o mcontext.o
/linux-4.1.27/drivers/spi/
Dspi-s3c24xx-fiq.S26 @ setup the calling registers.
28 @ fiq_rirq The base of the IRQ registers to find S3C2410_SRCPND
/linux-4.1.27/Documentation/devicetree/bindings/
Dmarvell.txt24 for memory mapped registers.
28 memory-mapped registers contained within the system controller
33 represent the address of the memory-mapped registers of devices
36 registers within the system controller chip.
103 registers for the node are interleaved within a single set
104 of registers. The "ethernet-block" level describes the
134 - reg : Should be <0>, <1>, or <2>, according to which registers
250 Represent the Discovery's MPSC DMA interrupt hardware registers
251 (SDMA cause and mask registers).
/linux-4.1.27/drivers/fmc/
DKconfig44 tristate "FMC mezzanine driver that registers a char device"
47 space to read and write registers using a char device. It
/linux-4.1.27/Documentation/devicetree/bindings/mailbox/
Domap-mailbox.txt7 communication is achieved through a set of registers for message storage and
8 interrupt configuration registers.
16 programmable through a set of interrupt configuration registers, and have a rx
21 The number of h/w fifo queues and interrupt lines dictate the usable registers.
/linux-4.1.27/Documentation/devicetree/bindings/serial/
Dnxp-lpc32xx-hsuart.txt5 - reg: Should contain registers location and length

123456