Searched refs:training_lane (Results 1 – 3 of 3) sorted by relevance
144 u8 training_lane[4]; member232 u32 training_lane);234 u32 training_lane);236 u32 training_lane);238 u32 training_lane);
471 u8 voltage_swing, pre_emphasis, training_lane; in exynos_dp_get_adjust_training_lane() local479 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | in exynos_dp_get_adjust_training_lane()483 training_lane |= DP_TRAIN_MAX_SWING_REACHED; in exynos_dp_get_adjust_training_lane()485 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; in exynos_dp_get_adjust_training_lane()487 dp->link_train.training_lane[lane] = training_lane; in exynos_dp_get_adjust_training_lane()494 u8 voltage_swing, pre_emphasis, training_lane; in exynos_dp_process_clock_recovery() local526 training_lane = exynos_dp_get_lane_link_training( in exynos_dp_process_clock_recovery()533 if (DPCD_VOLTAGE_SWING_GET(training_lane) == in exynos_dp_process_clock_recovery()535 DPCD_PRE_EMPHASIS_GET(training_lane) == in exynos_dp_process_clock_recovery()555 dp->link_train.training_lane[lane], lane); in exynos_dp_process_clock_recovery()[all …]
977 u32 training_lane) in exynos_dp_set_lane0_link_training() argument981 reg = training_lane; in exynos_dp_set_lane0_link_training()986 u32 training_lane) in exynos_dp_set_lane1_link_training() argument990 reg = training_lane; in exynos_dp_set_lane1_link_training()995 u32 training_lane) in exynos_dp_set_lane2_link_training() argument999 reg = training_lane; in exynos_dp_set_lane2_link_training()1004 u32 training_lane) in exynos_dp_set_lane3_link_training() argument1008 reg = training_lane; in exynos_dp_set_lane3_link_training()