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Searched refs:wrmsrl (Results 1 – 53 of 53) sorted by relevance

/linux-4.1.27/drivers/hv/
Dhv.c162 wrmsrl(HV_X64_MSR_GUEST_OS_ID, hv_context.guestid); in hv_init()
175 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_init()
192 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_init()
211 wrmsrl(HV_X64_MSR_GUEST_OS_ID, 0); in hv_cleanup()
215 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_cleanup()
278 wrmsrl(HV_X64_MSR_STIMER0_COUNT, current_tick); in hv_ce_set_next_event()
296 wrmsrl(HV_X64_MSR_STIMER0_CONFIG, timer_cfg.as_uint64); in hv_ce_setmode()
301 wrmsrl(HV_X64_MSR_STIMER0_COUNT, 0); in hv_ce_setmode()
302 wrmsrl(HV_X64_MSR_STIMER0_CONFIG, 0); in hv_ce_setmode()
427 wrmsrl(HV_X64_MSR_SIMP, simp.as_uint64); in hv_synic_init()
[all …]
Dvmbus_drv.c58 wrmsrl(HV_X64_MSR_CRASH_P0, regs->ip); in hyperv_panic_event()
59 wrmsrl(HV_X64_MSR_CRASH_P1, regs->ax); in hyperv_panic_event()
60 wrmsrl(HV_X64_MSR_CRASH_P2, regs->bx); in hyperv_panic_event()
61 wrmsrl(HV_X64_MSR_CRASH_P3, regs->cx); in hyperv_panic_event()
62 wrmsrl(HV_X64_MSR_CRASH_P4, regs->dx); in hyperv_panic_event()
67 wrmsrl(HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_CRASH_NOTIFY); in hyperv_panic_event()
650 wrmsrl(HV_X64_MSR_EOM, 0); in hv_process_timer_expiration()
707 wrmsrl(HV_X64_MSR_EOM, 0); in vmbus_on_msg_dpc()
/linux-4.1.27/arch/x86/oprofile/
Dop_model_amd.c157 wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl); in op_amd_handle_ibs()
186 wrmsrl(MSR_AMD64_IBSOPCTL, ctl); in op_amd_handle_ibs()
212 wrmsrl(MSR_AMD64_IBSFETCHCTL, val); in op_amd_start_ibs()
249 wrmsrl(MSR_AMD64_IBSOPCTL, val); in op_amd_start_ibs()
260 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0); in op_amd_stop_ibs()
264 wrmsrl(MSR_AMD64_IBSOPCTL, 0); in op_amd_stop_ibs()
283 wrmsrl(msrs->controls[i].addr, val); in op_mux_switch_ctrl()
357 wrmsrl(msrs->controls[i].addr, val); in op_amd_setup_ctrs()
362 wrmsrl(msrs->counters[i].addr, -1LL); in op_amd_setup_ctrs()
372 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]); in op_amd_setup_ctrs()
[all …]
Dop_model_ppro.c103 wrmsrl(msrs->controls[i].addr, val); in ppro_setup_ctrs()
108 wrmsrl(msrs->counters[i].addr, -1LL); in ppro_setup_ctrs()
115 wrmsrl(msrs->counters[i].addr, -reset_value[i]); in ppro_setup_ctrs()
119 wrmsrl(msrs->controls[i].addr, val); in ppro_setup_ctrs()
140 wrmsrl(msrs->counters[i].addr, -reset_value[i]); in ppro_check_ctrs()
167 wrmsrl(msrs->controls[i].addr, val); in ppro_start()
183 wrmsrl(msrs->controls[i].addr, val); in ppro_stop()
Dop_model_p4.c606 wrmsrl(p4_counters[VIRT_CTR(stag, i)].counter_address, in p4_setup_ctrs()
651 wrmsrl(p4_counters[real].counter_address, in p4_check_ctrs()
655 wrmsrl(p4_counters[real].counter_address, in p4_check_ctrs()
Dnmi_int.c222 wrmsrl(counters[i].addr, multiplex[virt].saved); in nmi_cpu_restore_mpx_registers()
363 wrmsrl(controls[i].addr, controls[i].saved); in nmi_cpu_restore_registers()
368 wrmsrl(counters[i].addr, counters[i].saved); in nmi_cpu_restore_registers()
/linux-4.1.27/arch/x86/kernel/cpu/
Dperf_event_intel_uncore_nhmex.c201 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL); in nhmex_uncore_msr_init_box()
215 wrmsrl(msr, config); in nhmex_uncore_msr_disable_box()
230 wrmsrl(msr, config); in nhmex_uncore_msr_enable_box()
236 wrmsrl(event->hw.config_base, 0); in nhmex_uncore_msr_disable_event()
244 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
246 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_uncore_msr_enable_event()
248 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
377 wrmsrl(reg1->reg, reg1->config); in nhmex_bbox_msr_enable_event()
378 wrmsrl(reg1->reg + 1, reg2->config); in nhmex_bbox_msr_enable_event()
380 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 | in nhmex_bbox_msr_enable_event()
[all …]
Dperf_event_intel_uncore_snb.c73 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); in snb_uncore_msr_enable_event()
75 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN); in snb_uncore_msr_enable_event()
80 wrmsrl(event->hw.config_base, 0); in snb_uncore_msr_disable_event()
86 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, in snb_uncore_msr_init_box()
569 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0); in nhm_uncore_msr_disable_box()
574 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC); in nhm_uncore_msr_enable_box()
582 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); in nhm_uncore_msr_enable_event()
584 wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN); in nhm_uncore_msr_enable_event()
Dperf_event_intel_lbr.c146 wrmsrl(MSR_LBR_SELECT, lbr_select); in __intel_pmu_lbr_enable()
160 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); in __intel_pmu_lbr_enable()
169 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); in __intel_pmu_lbr_disable()
177 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_32()
185 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_64()
186 wrmsrl(x86_pmu.lbr_to + i, 0); in intel_pmu_lbr_reset_64()
233 wrmsrl(x86_pmu.lbr_from + lbr_idx, task_ctx->lbr_from[i]); in __intel_pmu_lbr_restore()
234 wrmsrl(x86_pmu.lbr_to + lbr_idx, task_ctx->lbr_to[i]); in __intel_pmu_lbr_restore()
Dperf_event_knc.c163 wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); in knc_pmu_disable_all()
172 wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); in knc_pmu_enable_all()
209 wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_OVF_CONTROL, ack); in knc_pmu_ack_status()
Dperf_event_intel_pt.c212 wrmsrl(MSR_IA32_RTIT_CTL, reg); in pt_config()
224 wrmsrl(MSR_IA32_RTIT_CTL, ctl); in pt_config_start()
243 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, virt_to_phys(buf)); in pt_config_buffer()
247 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, reg); in pt_config_buffer()
558 wrmsrl(MSR_IA32_RTIT_STATUS, status); in pt_handle_status()
914 wrmsrl(MSR_IA32_RTIT_STATUS, 0); in intel_pt_interrupt()
938 wrmsrl(MSR_IA32_RTIT_STATUS, 0); in pt_event_start()
Dperf_event_intel_uncore_snbep.c331 wrmsrl(msr, config); in snbep_uncore_msr_disable_box()
344 wrmsrl(msr, config); in snbep_uncore_msr_enable_box()
354 wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0)); in snbep_uncore_msr_enable_event()
356 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); in snbep_uncore_msr_enable_event()
364 wrmsrl(hwc->config_base, hwc->config); in snbep_uncore_msr_disable_event()
372 wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT); in snbep_uncore_msr_init_box()
1156 wrmsrl(msr, IVBEP_PMON_BOX_CTL_INT); in ivbep_uncore_msr_init_box()
1407 wrmsrl(reg1->reg, filter & 0xffffffff); in ivbep_cbox_enable_event()
1408 wrmsrl(reg1->reg + 6, filter >> 32); in ivbep_cbox_enable_event()
1411 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); in ivbep_cbox_enable_event()
[all …]
Dcommon.c395 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); in load_percpu_segment()
1209 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); in syscall_init()
1210 wrmsrl(MSR_LSTAR, system_call); in syscall_init()
1213 wrmsrl(MSR_CSTAR, ia32_cstar_target); in syscall_init()
1224 wrmsrl(MSR_CSTAR, ignore_sysret); in syscall_init()
1231 wrmsrl(MSR_SYSCALL_MASK, in syscall_init()
1397 wrmsrl(MSR_FS_BASE, 0); in cpu_init()
1398 wrmsrl(MSR_KERNEL_GS_BASE, 0); in cpu_init()
Dperf_event_p6.c144 wrmsrl(MSR_P6_EVNTSEL0, val); in p6_pmu_disable_all()
154 wrmsrl(MSR_P6_EVNTSEL0, val); in p6_pmu_enable_all()
Dperf_event.h18 #undef wrmsrl
19 #define wrmsrl(msr, val) \
724 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); in __x86_pmu_enable_event()
725 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); in __x86_pmu_enable_event()
740 wrmsrl(hwc->config_base, hwc->config); in x86_pmu_disable_event()
Dperf_event_amd_uncore.c98 wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count)); in amd_uncore_start()
101 wrmsrl(hwc->config_base, (hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE)); in amd_uncore_start()
109 wrmsrl(hwc->config_base, hwc->config); in amd_uncore_stop()
Dperf_event_intel.c1253 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); in __intel_pmu_disable_all()
1275 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, in __intel_pmu_enable_all()
1350 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); in intel_pmu_nhm_workaround()
1351 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); in intel_pmu_nhm_workaround()
1354 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); in intel_pmu_nhm_workaround()
1355 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); in intel_pmu_nhm_workaround()
1365 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); in intel_pmu_nhm_workaround()
1387 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); in intel_pmu_ack_status()
1399 wrmsrl(hwc->config_base, ctrl_val); in intel_pmu_disable_fixed()
1468 wrmsrl(hwc->config_base, ctrl_val); in intel_pmu_enable_fixed()
[all …]
Dperf_event_intel_ds.c715 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_disable()
725 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_enable_all()
733 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); in intel_pmu_pebs_disable_all()
1115 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds); in perf_restore_debug_store()
Dperf_event_amd_ibs.c340 wrmsrl(hwc->config_base, hwc->config | config | perf_ibs->enable_mask); in perf_ibs_enable_event()
354 wrmsrl(hwc->config_base, config); in perf_ibs_disable_event()
356 wrmsrl(hwc->config_base, config); in perf_ibs_disable_event()
Dperf_event_intel_cqm.c989 wrmsrl(MSR_IA32_PQR_ASSOC, state->rmid); in intel_cqm_event_start()
1009 wrmsrl(MSR_IA32_PQR_ASSOC, 0); in intel_cqm_event_stop()
Dintel.c493 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); in init_intel()
Dperf_event.c587 wrmsrl(x86_pmu_config_addr(idx), val); in x86_pmu_disable_all()
1120 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); in x86_perf_event_set_period()
1128 wrmsrl(hwc->event_base, in x86_perf_event_set_period()
Dperf_event_p4.c862 wrmsrl(hwc->config_base, v & ~P4_CCCR_OVF); in p4_pmu_clear_cccr_ovf()
/linux-4.1.27/arch/x86/power/
Dcpu.c169 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); in __restore_processor_state()
179 wrmsrl(MSR_EFER, ctxt->efer); in __restore_processor_state()
220 wrmsrl(MSR_FS_BASE, ctxt->fs_base); in __restore_processor_state()
221 wrmsrl(MSR_GS_BASE, ctxt->gs_base); in __restore_processor_state()
222 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); in __restore_processor_state()
/linux-4.1.27/arch/x86/include/asm/
Dvirtext.h119 wrmsrl(MSR_VM_HSAVE_PA, 0); in cpu_svm_disable()
121 wrmsrl(MSR_EFER, efer & ~EFER_SVME); in cpu_svm_disable()
Dmsr.h155 #define wrmsrl(msr, val) \ macro
251 wrmsrl(msr_no, q); in wrmsrl_on_cpu()
Dapic.h168 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); in native_x2apic_icr_write()
Dprocessor.h771 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); in update_debugctlmsr()
Dparavirt.h156 #define wrmsrl(msr, val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32) macro
/linux-4.1.27/drivers/video/fbdev/geode/
Dvideo_gx.c158 wrmsrl(MSR_GLCP_DOTPLL, dotpll); in gx_set_dclk_frequency()
166 wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll); in gx_set_dclk_frequency()
170 wrmsrl(MSR_GLCP_DOTPLL, dotpll); in gx_set_dclk_frequency()
190 wrmsrl(MSR_GX_MSR_PADSEL, val); in gx_configure_tft()
Dlxfb_ops.c378 wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval); in lx_set_mode()
434 wrmsrl(MSR_LX_SPARE_MSR, msrval); in lx_set_mode()
673 wrmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare); in lx_restore_display_ctlr()
737 wrmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg); in lx_restore_video_proc()
738 wrmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel); in lx_restore_video_proc()
Dsuspend_gx.c142 wrmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel); in gx_restore_video_proc()
/linux-4.1.27/drivers/cpufreq/
Dlonghaul.c147 wrmsrl(MSR_VIA_BCR2, bcr2.val); in do_longhaul1()
156 wrmsrl(MSR_VIA_BCR2, bcr2.val); in do_longhaul1()
183 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
197 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
202 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
215 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
220 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
234 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
Dpowernow-k7.c230 wrmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val); in change_FID()
245 wrmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val); in change_VID()
De_powersaver.c234 wrmsrl(MSR_IA32_MISC_ENABLE, val); in eps_cpu_init()
Dintel_pstate.c489 wrmsrl( MSR_PM_ENABLE, 0x1); in intel_pstate_hwp_enable()
/linux-4.1.27/arch/x86/kernel/
Dkvm.c313 wrmsrl(MSR_KVM_STEAL_TIME, (slow_virt_to_phys(st) | KVM_MSR_ENABLED)); in kvm_register_steal_time()
345 wrmsrl(MSR_KVM_ASYNC_PF_EN, pa | KVM_ASYNC_PF_ENABLED); in kvm_guest_cpu_init()
358 wrmsrl(MSR_KVM_PV_EOI_EN, pa); in kvm_guest_cpu_init()
370 wrmsrl(MSR_KVM_ASYNC_PF_EN, 0); in kvm_pv_disable_apf()
385 wrmsrl(MSR_KVM_PV_EOI_EN, 0); in kvm_pv_guest_cpu_reboot()
444 wrmsrl(MSR_KVM_PV_EOI_EN, 0); in kvm_guest_cpu_offline()
Dreboot_fixups_32.c29 wrmsrl(MSR_DIVIL_SOFT_RESET, 1ULL); in cs5536_warm_reset()
Dmmconf-fam10h_64.c213 wrmsrl(address, val); in fam10h_check_enable_mmcfg()
Dprocess_64.c381 wrmsrl(MSR_FS_BASE, next->fs); in __switch_to()
392 wrmsrl(MSR_KERNEL_GS_BASE, next->gs); in __switch_to()
/linux-4.1.27/arch/x86/kernel/cpu/mcheck/
Dmce_intel.c135 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in cmci_toggle_interrupt_mode()
274 wrmsrl(MSR_IA32_MCx_CTL2(i), val); in cmci_discover()
329 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in __cmci_disable_bank()
Dmce.c425 wrmsrl(msr, v); in mce_wrmsrl()
1472 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); in __mcheck_cpu_init_generic()
1473 wrmsrl(MSR_IA32_MCx_STATUS(i), 0); in __mcheck_cpu_init_generic()
1566 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); in __mcheck_cpu_apply_quirks()
1574 wrmsrl(MSR_K7_HWCR, hwcr); in __mcheck_cpu_apply_quirks()
2051 wrmsrl(MSR_IA32_MCx_CTL(i), 0); in mce_disable_error_reporting()
2354 wrmsrl(MSR_IA32_MCx_CTL(i), 0); in mce_disable_cpu()
2372 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); in mce_reenable_cpu()
Dmce_amd.c332 wrmsrl(MSR_IA32_MCx_STATUS(bank), 0); in amd_threshold_interrupt()
/linux-4.1.27/drivers/platform/x86/
Dintel_ips.c397 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); in ips_cpu_raise()
402 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); in ips_cpu_raise()
432 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); in ips_cpu_lower()
437 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); in ips_cpu_lower()
455 wrmsrl(IA32_PERF_CTL, perf_ctl); in do_enable_cpu_turbo()
493 wrmsrl(IA32_PERF_CTL, perf_ctl); in do_disable_cpu_turbo()
1708 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); in ips_remove()
1709 wrmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); in ips_remove()
/linux-4.1.27/drivers/idle/
Dintel_idle.c750 wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); in auto_demotion_disable()
758 wrmsrl(MSR_IA32_POWER_CTL, msr_bits); in c1e_promotion_disable()
1003 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0); in intel_idle_cpuidle_driver_init()
1004 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0); in intel_idle_cpuidle_driver_init()
/linux-4.1.27/drivers/thermal/
Dx86_pkg_temp_thermal.c340 wrmsrl(MSR_IA32_PACKAGE_THERM_STATUS, in pkg_temp_thermal_threshold_work_fn()
345 wrmsrl(MSR_IA32_PACKAGE_THERM_STATUS, in pkg_temp_thermal_threshold_work_fn()
/linux-4.1.27/arch/x86/kernel/apic/
Dapic.c468 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); in lapic_next_deadline()
1441 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); in __x2apic_disable()
1442 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); in __x2apic_disable()
1453 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); in __x2apic_enable()
/linux-4.1.27/arch/x86/pci/
Damd_bus.c336 wrmsrl(MSR_AMD64_NB_CFG, reg); in enable_pci_io_ecs()
/linux-4.1.27/arch/x86/platform/olpc/
Dolpc-xo1-sci.c328 wrmsrl(0x51400020, lo); in setup_sci_interrupt()
/linux-4.1.27/arch/x86/kvm/
Dsvm.c631 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); in svm_hardware_disable()
669 wrmsrl(MSR_EFER, efer | EFER_SVME); in svm_hardware_enable()
671 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); in svm_hardware_enable()
674 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); in svm_hardware_enable()
1324 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio); in svm_vcpu_load()
1337 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); in svm_vcpu_put()
1345 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); in svm_vcpu_put()
3968 wrmsrl(MSR_GS_BASE, svm->host.gs_base); in svm_vcpu_run()
Dvmx.c1683 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); in add_atomic_switch_msr()
1856 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); in vmx_save_host_state()
1895 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); in __vmx_load_host_state()
1898 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); in __vmx_load_host_state()
2923 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); in hardware_enable()
Dx86.c194 wrmsrl(shared_msrs_global.msrs[slot], values->host); in kvm_on_user_return()
/linux-4.1.27/arch/x86/mm/
Dpat.c245 wrmsrl(MSR_IA32_CR_PAT, pat); in pat_init()