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Searched refs:CLK_PDMA1 (Results 1 – 62 of 62) sorted by relevance

/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
Dexynos5250.h82 #define CLK_PDMA1 276 macro
Dexynos5420.h123 #define CLK_PDMA1 363 macro
Ds5pv210.h117 #define CLK_PDMA1 96 macro
Dexynos4.h133 #define CLK_PDMA1 293 macro
Dexynos3250.h204 #define CLK_PDMA1 200 macro
Dexynos4415.h264 #define CLK_PDMA1 269 macro
Dexynos5433.h574 #define CLK_PDMA1 64 macro
/linux-4.4.14/include/dt-bindings/clock/
Dexynos5250.h82 #define CLK_PDMA1 276 macro
Dexynos5420.h123 #define CLK_PDMA1 363 macro
Ds5pv210.h117 #define CLK_PDMA1 96 macro
Dexynos4.h133 #define CLK_PDMA1 293 macro
Dexynos3250.h204 #define CLK_PDMA1 200 macro
Dexynos4415.h264 #define CLK_PDMA1 269 macro
Dexynos5433.h574 #define CLK_PDMA1 64 macro
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
Dexynos5250.h82 #define CLK_PDMA1 276 macro
Dexynos5420.h123 #define CLK_PDMA1 363 macro
Ds5pv210.h117 #define CLK_PDMA1 96 macro
Dexynos4.h133 #define CLK_PDMA1 293 macro
Dexynos3250.h204 #define CLK_PDMA1 200 macro
Dexynos4415.h264 #define CLK_PDMA1 269 macro
Dexynos5433.h574 #define CLK_PDMA1 64 macro
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
Dexynos5250.h82 #define CLK_PDMA1 276 macro
Dexynos5420.h123 #define CLK_PDMA1 363 macro
Ds5pv210.h117 #define CLK_PDMA1 96 macro
Dexynos4.h133 #define CLK_PDMA1 293 macro
Dexynos3250.h204 #define CLK_PDMA1 200 macro
Dexynos4415.h264 #define CLK_PDMA1 269 macro
Dexynos5433.h574 #define CLK_PDMA1 64 macro
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
Dexynos5250.h82 #define CLK_PDMA1 276 macro
Dexynos5420.h123 #define CLK_PDMA1 363 macro
Ds5pv210.h117 #define CLK_PDMA1 96 macro
Dexynos4.h133 #define CLK_PDMA1 293 macro
Dexynos3250.h204 #define CLK_PDMA1 200 macro
Dexynos4415.h264 #define CLK_PDMA1 269 macro
Dexynos5433.h574 #define CLK_PDMA1 64 macro
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
Dexynos5250.h82 #define CLK_PDMA1 276 macro
Dexynos5420.h123 #define CLK_PDMA1 363 macro
Ds5pv210.h117 #define CLK_PDMA1 96 macro
Dexynos4.h133 #define CLK_PDMA1 293 macro
Dexynos3250.h204 #define CLK_PDMA1 200 macro
Dexynos4415.h264 #define CLK_PDMA1 269 macro
Dexynos5433.h574 #define CLK_PDMA1 64 macro
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
Dexynos5250.h82 #define CLK_PDMA1 276 macro
Dexynos5420.h123 #define CLK_PDMA1 363 macro
Ds5pv210.h117 #define CLK_PDMA1 96 macro
Dexynos4.h133 #define CLK_PDMA1 293 macro
Dexynos3250.h204 #define CLK_PDMA1 200 macro
Dexynos4415.h264 #define CLK_PDMA1 269 macro
Dexynos5433.h574 #define CLK_PDMA1 64 macro
/linux-4.4.14/drivers/clk/samsung/
Dclk-exynos5250.c602 GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
Dclk-s5pv210.c673 GATE(CLK_PDMA1, "pdma1", "dout_hclkp", CLK_GATE_IP0, 4, 0, 0),
Dclk-exynos4415.c832 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
Dclk-exynos3250.c635 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
Dclk-exynos5420.c1012 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
Dclk-exynos4.c970 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
Dclk-exynos5433.c2322 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
/linux-4.4.14/arch/arm/boot/dts/
Dexynos3250.dtsi390 clocks = <&cmu CLK_PDMA1>;
Ds5pv210.dtsi153 clocks = <&clocks CLK_PDMA1>;
Dexynos4415.dtsi404 clocks = <&cmu CLK_PDMA1>;
Dexynos4.dtsi669 clocks = <&clock CLK_PDMA1>;
Dexynos5250.dtsi687 clocks = <&clock CLK_PDMA1>;
Dexynos5420.dtsi360 clocks = <&clock CLK_PDMA1>;