| /linux-4.4.14/include/dt-bindings/clock/ |
| D | exynos4.h | 190 #define CLK_PIXELASYNCM0 351 macro
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| D | exynos3250.h | 166 #define CLK_PIXELASYNCM0 162 macro
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| D | exynos4415.h | 223 #define CLK_PIXELASYNCM0 228 macro
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| /linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 190 #define CLK_PIXELASYNCM0 351 macro
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| D | exynos3250.h | 166 #define CLK_PIXELASYNCM0 162 macro
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| D | exynos4415.h | 223 #define CLK_PIXELASYNCM0 228 macro
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| /linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 190 #define CLK_PIXELASYNCM0 351 macro
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| D | exynos3250.h | 166 #define CLK_PIXELASYNCM0 162 macro
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| D | exynos4415.h | 223 #define CLK_PIXELASYNCM0 228 macro
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| /linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 190 #define CLK_PIXELASYNCM0 351 macro
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| D | exynos3250.h | 166 #define CLK_PIXELASYNCM0 162 macro
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| D | exynos4415.h | 223 #define CLK_PIXELASYNCM0 228 macro
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| /linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 190 #define CLK_PIXELASYNCM0 351 macro
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| D | exynos3250.h | 166 #define CLK_PIXELASYNCM0 162 macro
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| D | exynos4415.h | 223 #define CLK_PIXELASYNCM0 228 macro
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| /linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 190 #define CLK_PIXELASYNCM0 351 macro
|
| D | exynos3250.h | 166 #define CLK_PIXELASYNCM0 162 macro
|
| D | exynos4415.h | 223 #define CLK_PIXELASYNCM0 228 macro
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| /linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 190 #define CLK_PIXELASYNCM0 351 macro
|
| D | exynos3250.h | 166 #define CLK_PIXELASYNCM0 162 macro
|
| D | exynos4415.h | 223 #define CLK_PIXELASYNCM0 228 macro
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| /linux-4.4.14/arch/arm/boot/dts/ |
| D | exynos4210.dtsi | 194 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
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| D | exynos4x12.dtsi | 124 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
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| /linux-4.4.14/drivers/clk/samsung/ |
| D | clk-exynos4415.c | 773 GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_aclk_160", GATE_IP_CAM,
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| D | clk-exynos3250.c | 565 GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
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| D | clk-exynos4.c | 951 GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
|