| /linux-4.4.14/include/dt-bindings/clock/ |
| D | exynos4.h | 241 #define CLK_PPMULEFT 400 macro
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| D | exynos3250.h | 134 #define CLK_PPMULEFT 130 macro
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| D | exynos4415.h | 178 #define CLK_PPMULEFT 183 macro
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| /linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 241 #define CLK_PPMULEFT 400 macro
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| D | exynos3250.h | 134 #define CLK_PPMULEFT 130 macro
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| D | exynos4415.h | 178 #define CLK_PPMULEFT 183 macro
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| /linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 241 #define CLK_PPMULEFT 400 macro
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| D | exynos3250.h | 134 #define CLK_PPMULEFT 130 macro
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| D | exynos4415.h | 178 #define CLK_PPMULEFT 183 macro
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| /linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 241 #define CLK_PPMULEFT 400 macro
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| D | exynos3250.h | 134 #define CLK_PPMULEFT 130 macro
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| D | exynos4415.h | 178 #define CLK_PPMULEFT 183 macro
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| /linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 241 #define CLK_PPMULEFT 400 macro
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| D | exynos3250.h | 134 #define CLK_PPMULEFT 130 macro
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| D | exynos4415.h | 178 #define CLK_PPMULEFT 183 macro
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| /linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 241 #define CLK_PPMULEFT 400 macro
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| D | exynos3250.h | 134 #define CLK_PPMULEFT 130 macro
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| D | exynos4415.h | 178 #define CLK_PPMULEFT 183 macro
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| /linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| D | exynos4.h | 241 #define CLK_PPMULEFT 400 macro
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| D | exynos3250.h | 134 #define CLK_PPMULEFT 130 macro
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| D | exynos4415.h | 178 #define CLK_PPMULEFT 183 macro
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| /linux-4.4.14/Documentation/devicetree/bindings/devfreq/event/ |
| D | exynos-ppmu.txt | 52 clocks = <&cmu CLK_PPMULEFT>;
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| /linux-4.4.14/arch/arm/boot/dts/ |
| D | exynos3250.dtsi | 646 clocks = <&cmu CLK_PPMULEFT>;
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| D | exynos4.dtsi | 781 clocks = <&clock CLK_PPMULEFT>;
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| /linux-4.4.14/drivers/clk/samsung/ |
| D | clk-exynos4415.c | 585 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
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| D | clk-exynos3250.c | 438 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
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| D | clk-exynos4.c | 846 GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
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