Searched refs:CLK_RESET_SOURCE_CSITE (Results 1 – 1 of 1) sorted by relevance
150 #define CLK_RESET_SOURCE_CSITE 0x1d4 macro1270 readl(clk_base + CLK_RESET_SOURCE_CSITE); in tegra30_cpu_clock_suspend()1271 writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE); in tegra30_cpu_clock_suspend()1320 clk_base + CLK_RESET_SOURCE_CSITE); in tegra30_cpu_clock_resume()