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Searched refs:CLK_SCLK_FIMD1 (Results 1 – 26 of 26) sorted by relevance

/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
Dexynos5250.h32 #define CLK_SCLK_FIMD1 133 macro
Dexynos5420.h49 #define CLK_SCLK_FIMD1 147 macro
Dexynos4.h79 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ macro
/linux-4.4.14/include/dt-bindings/clock/
Dexynos5250.h32 #define CLK_SCLK_FIMD1 133 macro
Dexynos5420.h49 #define CLK_SCLK_FIMD1 147 macro
Dexynos4.h79 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ macro
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
Dexynos5250.h32 #define CLK_SCLK_FIMD1 133 macro
Dexynos5420.h49 #define CLK_SCLK_FIMD1 147 macro
Dexynos4.h79 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ macro
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
Dexynos5250.h32 #define CLK_SCLK_FIMD1 133 macro
Dexynos5420.h49 #define CLK_SCLK_FIMD1 147 macro
Dexynos4.h79 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ macro
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
Dexynos5250.h32 #define CLK_SCLK_FIMD1 133 macro
Dexynos5420.h49 #define CLK_SCLK_FIMD1 147 macro
Dexynos4.h79 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ macro
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
Dexynos5250.h32 #define CLK_SCLK_FIMD1 133 macro
Dexynos5420.h49 #define CLK_SCLK_FIMD1 147 macro
Dexynos4.h79 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ macro
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
Dexynos5250.h32 #define CLK_SCLK_FIMD1 133 macro
Dexynos5420.h49 #define CLK_SCLK_FIMD1 147 macro
Dexynos4.h79 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ macro
/linux-4.4.14/drivers/clk/samsung/
Dclk-exynos5250.c503 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
Dclk-exynos5420.c992 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
Dclk-exynos4.c1085 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,
/linux-4.4.14/arch/arm/boot/dts/
Dexynos5250.dtsi1059 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
Dexynos5420.dtsi1135 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;