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Searched refs:CLK_SCLK_UART0 (Results 1 – 76 of 76) sorted by relevance

/linux-4.4.14/include/dt-bindings/clock/
Dexynos5410.h13 #define CLK_SCLK_UART0 128 macro
Dexynos5250.h45 #define CLK_SCLK_UART0 146 macro
Dexynos7-clk.h40 #define CLK_SCLK_UART0 3 macro
Dexynos5420.h30 #define CLK_SCLK_UART0 128 macro
Dexynos4.h67 #define CLK_SCLK_UART0 151 macro
Dexynos3250.h251 #define CLK_SCLK_UART0 247 macro
Dexynos4415.h327 #define CLK_SCLK_UART0 368 macro
Dexynos5433.h440 #define CLK_SCLK_UART0 36 macro
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
Dexynos5410.h13 #define CLK_SCLK_UART0 128 macro
Dexynos5250.h45 #define CLK_SCLK_UART0 146 macro
Dexynos7-clk.h40 #define CLK_SCLK_UART0 3 macro
Dexynos5420.h30 #define CLK_SCLK_UART0 128 macro
Dexynos4.h67 #define CLK_SCLK_UART0 151 macro
Dexynos3250.h251 #define CLK_SCLK_UART0 247 macro
Dexynos4415.h327 #define CLK_SCLK_UART0 368 macro
Dexynos5433.h440 #define CLK_SCLK_UART0 36 macro
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
Dexynos5410.h13 #define CLK_SCLK_UART0 128 macro
Dexynos5250.h45 #define CLK_SCLK_UART0 146 macro
Dexynos7-clk.h40 #define CLK_SCLK_UART0 3 macro
Dexynos5420.h30 #define CLK_SCLK_UART0 128 macro
Dexynos4.h67 #define CLK_SCLK_UART0 151 macro
Dexynos3250.h251 #define CLK_SCLK_UART0 247 macro
Dexynos4415.h327 #define CLK_SCLK_UART0 368 macro
Dexynos5433.h440 #define CLK_SCLK_UART0 36 macro
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
Dexynos5410.h13 #define CLK_SCLK_UART0 128 macro
Dexynos5250.h45 #define CLK_SCLK_UART0 146 macro
Dexynos7-clk.h40 #define CLK_SCLK_UART0 3 macro
Dexynos5420.h30 #define CLK_SCLK_UART0 128 macro
Dexynos4.h67 #define CLK_SCLK_UART0 151 macro
Dexynos3250.h251 #define CLK_SCLK_UART0 247 macro
Dexynos4415.h327 #define CLK_SCLK_UART0 368 macro
Dexynos5433.h440 #define CLK_SCLK_UART0 36 macro
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
Dexynos5410.h13 #define CLK_SCLK_UART0 128 macro
Dexynos5250.h45 #define CLK_SCLK_UART0 146 macro
Dexynos7-clk.h40 #define CLK_SCLK_UART0 3 macro
Dexynos5420.h30 #define CLK_SCLK_UART0 128 macro
Dexynos4.h67 #define CLK_SCLK_UART0 151 macro
Dexynos3250.h251 #define CLK_SCLK_UART0 247 macro
Dexynos4415.h327 #define CLK_SCLK_UART0 368 macro
Dexynos5433.h440 #define CLK_SCLK_UART0 36 macro
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
Dexynos5410.h13 #define CLK_SCLK_UART0 128 macro
Dexynos5250.h45 #define CLK_SCLK_UART0 146 macro
Dexynos7-clk.h40 #define CLK_SCLK_UART0 3 macro
Dexynos5420.h30 #define CLK_SCLK_UART0 128 macro
Dexynos4.h67 #define CLK_SCLK_UART0 151 macro
Dexynos3250.h251 #define CLK_SCLK_UART0 247 macro
Dexynos4415.h327 #define CLK_SCLK_UART0 368 macro
Dexynos5433.h440 #define CLK_SCLK_UART0 36 macro
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
Dexynos5410.h13 #define CLK_SCLK_UART0 128 macro
Dexynos5250.h45 #define CLK_SCLK_UART0 146 macro
Dexynos7-clk.h40 #define CLK_SCLK_UART0 3 macro
Dexynos5420.h30 #define CLK_SCLK_UART0 128 macro
Dexynos4.h67 #define CLK_SCLK_UART0 151 macro
Dexynos3250.h251 #define CLK_SCLK_UART0 247 macro
Dexynos4415.h327 #define CLK_SCLK_UART0 368 macro
Dexynos5433.h440 #define CLK_SCLK_UART0 36 macro
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Dexynos5410-clock.txt43 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
Dexynos3250-clock.txt55 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
Dexynos5433-clock.txt457 <&cmu_peric CLK_SCLK_UART0>;
/linux-4.4.14/drivers/clk/samsung/
Dclk-exynos5410.c162 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
Dclk-exynos5250.c531 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
Dclk-exynos4415.c763 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
Dclk-exynos3250.c557 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
Dclk-exynos7.c369 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
Dclk-exynos5420.c949 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
Dclk-exynos4.c910 GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
Dclk-exynos5433.c1722 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
/linux-4.4.14/arch/arm/boot/dts/
Dexynos5410.dtsi198 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
Dexynos3250.dtsi436 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
Dexynos3250-monk.dts441 assigned-clocks = <&cmu CLK_SCLK_UART0>;
Dexynos4415.dtsi428 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
Dexynos3250-rinato.dts618 assigned-clocks = <&cmu CLK_SCLK_UART0>;
Dexynos4.dtsi432 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
Dexynos5250.dtsi1072 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
Dexynos5420.dtsi1150 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
/linux-4.4.14/arch/arm64/boot/dts/exynos/
Dexynos7.dtsi143 <&clock_top0 CLK_SCLK_UART0>;