| /linux-4.4.14/include/dt-bindings/clock/ |
| D | exynos5410.h | 14 #define CLK_SCLK_UART1 129 macro
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| D | exynos5250.h | 46 #define CLK_SCLK_UART1 147 macro
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| D | exynos7-clk.h | 41 #define CLK_SCLK_UART1 4 macro
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| D | exynos5420.h | 31 #define CLK_SCLK_UART1 129 macro
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| D | exynos4.h | 68 #define CLK_SCLK_UART1 152 macro
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| D | exynos3250.h | 250 #define CLK_SCLK_UART1 246 macro
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| D | exynos4415.h | 326 #define CLK_SCLK_UART1 367 macro
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| D | exynos5433.h | 439 #define CLK_SCLK_UART1 35 macro
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| /linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 14 #define CLK_SCLK_UART1 129 macro
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| D | exynos5250.h | 46 #define CLK_SCLK_UART1 147 macro
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| D | exynos7-clk.h | 41 #define CLK_SCLK_UART1 4 macro
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| D | exynos5420.h | 31 #define CLK_SCLK_UART1 129 macro
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| D | exynos4.h | 68 #define CLK_SCLK_UART1 152 macro
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| D | exynos3250.h | 250 #define CLK_SCLK_UART1 246 macro
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| D | exynos4415.h | 326 #define CLK_SCLK_UART1 367 macro
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| D | exynos5433.h | 439 #define CLK_SCLK_UART1 35 macro
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| /linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 14 #define CLK_SCLK_UART1 129 macro
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| D | exynos5250.h | 46 #define CLK_SCLK_UART1 147 macro
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| D | exynos7-clk.h | 41 #define CLK_SCLK_UART1 4 macro
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| D | exynos5420.h | 31 #define CLK_SCLK_UART1 129 macro
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| D | exynos4.h | 68 #define CLK_SCLK_UART1 152 macro
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| D | exynos3250.h | 250 #define CLK_SCLK_UART1 246 macro
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| D | exynos4415.h | 326 #define CLK_SCLK_UART1 367 macro
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| D | exynos5433.h | 439 #define CLK_SCLK_UART1 35 macro
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| /linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 14 #define CLK_SCLK_UART1 129 macro
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| D | exynos5250.h | 46 #define CLK_SCLK_UART1 147 macro
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| D | exynos7-clk.h | 41 #define CLK_SCLK_UART1 4 macro
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| D | exynos5420.h | 31 #define CLK_SCLK_UART1 129 macro
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| D | exynos4.h | 68 #define CLK_SCLK_UART1 152 macro
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| D | exynos3250.h | 250 #define CLK_SCLK_UART1 246 macro
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| D | exynos4415.h | 326 #define CLK_SCLK_UART1 367 macro
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| D | exynos5433.h | 439 #define CLK_SCLK_UART1 35 macro
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| /linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 14 #define CLK_SCLK_UART1 129 macro
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| D | exynos5250.h | 46 #define CLK_SCLK_UART1 147 macro
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| D | exynos7-clk.h | 41 #define CLK_SCLK_UART1 4 macro
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| D | exynos5420.h | 31 #define CLK_SCLK_UART1 129 macro
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| D | exynos4.h | 68 #define CLK_SCLK_UART1 152 macro
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| D | exynos3250.h | 250 #define CLK_SCLK_UART1 246 macro
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| D | exynos4415.h | 326 #define CLK_SCLK_UART1 367 macro
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| D | exynos5433.h | 439 #define CLK_SCLK_UART1 35 macro
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| /linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 14 #define CLK_SCLK_UART1 129 macro
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| D | exynos5250.h | 46 #define CLK_SCLK_UART1 147 macro
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| D | exynos7-clk.h | 41 #define CLK_SCLK_UART1 4 macro
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| D | exynos5420.h | 31 #define CLK_SCLK_UART1 129 macro
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| D | exynos4.h | 68 #define CLK_SCLK_UART1 152 macro
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| D | exynos3250.h | 250 #define CLK_SCLK_UART1 246 macro
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| D | exynos4415.h | 326 #define CLK_SCLK_UART1 367 macro
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| D | exynos5433.h | 439 #define CLK_SCLK_UART1 35 macro
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| /linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/ |
| D | exynos5410.h | 14 #define CLK_SCLK_UART1 129 macro
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| D | exynos5250.h | 46 #define CLK_SCLK_UART1 147 macro
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| D | exynos7-clk.h | 41 #define CLK_SCLK_UART1 4 macro
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| D | exynos5420.h | 31 #define CLK_SCLK_UART1 129 macro
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| D | exynos4.h | 68 #define CLK_SCLK_UART1 152 macro
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| D | exynos3250.h | 250 #define CLK_SCLK_UART1 246 macro
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| D | exynos4415.h | 326 #define CLK_SCLK_UART1 367 macro
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| D | exynos5433.h | 439 #define CLK_SCLK_UART1 35 macro
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| /linux-4.4.14/drivers/clk/samsung/ |
| D | clk-exynos5410.c | 164 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
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| D | clk-exynos5250.c | 533 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
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| D | clk-exynos4415.c | 761 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
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| D | clk-exynos3250.c | 555 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
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| D | clk-exynos7.c | 367 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
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| D | clk-exynos5420.c | 951 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
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| D | clk-exynos4.c | 912 GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
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| D | clk-exynos5433.c | 1720 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
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| /linux-4.4.14/arch/arm/boot/dts/ |
| D | exynos5410.dtsi | 207 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| D | exynos3250.dtsi | 447 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
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| D | exynos4415.dtsi | 437 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
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| D | exynos4.dtsi | 443 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| D | exynos5250.dtsi | 1077 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| D | exynos5420.dtsi | 1155 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| /linux-4.4.14/arch/arm64/boot/dts/exynos/ |
| D | exynos7.dtsi | 153 <&clock_top0 CLK_SCLK_UART1>,
|