| /linux-4.4.14/include/dt-bindings/clock/ |
| D | pistachio-clk.h | 45 #define CLK_SPI0 51 macro
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| D | exynos5250.h | 110 #define CLK_SPI0 304 macro
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| D | exynos5420.h | 80 #define CLK_SPI0 271 macro
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| D | s5pv210.h | 168 #define CLK_SPI0 147 macro
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| D | exynos4.h | 167 #define CLK_SPI0 327 macro
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| D | exynos3250.h | 210 #define CLK_SPI0 206 macro
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| D | exynos4415.h | 273 #define CLK_SPI0 278 macro
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| /linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/ |
| D | pistachio-clk.h | 45 #define CLK_SPI0 51 macro
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| D | exynos5250.h | 110 #define CLK_SPI0 304 macro
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| D | exynos5420.h | 80 #define CLK_SPI0 271 macro
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| D | s5pv210.h | 168 #define CLK_SPI0 147 macro
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| D | exynos4.h | 167 #define CLK_SPI0 327 macro
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| D | exynos3250.h | 210 #define CLK_SPI0 206 macro
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| D | exynos4415.h | 273 #define CLK_SPI0 278 macro
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| /linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/ |
| D | pistachio-clk.h | 45 #define CLK_SPI0 51 macro
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| D | exynos5250.h | 110 #define CLK_SPI0 304 macro
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| D | exynos5420.h | 80 #define CLK_SPI0 271 macro
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| D | s5pv210.h | 168 #define CLK_SPI0 147 macro
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| D | exynos4.h | 167 #define CLK_SPI0 327 macro
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| D | exynos3250.h | 210 #define CLK_SPI0 206 macro
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| D | exynos4415.h | 273 #define CLK_SPI0 278 macro
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| /linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| D | pistachio-clk.h | 45 #define CLK_SPI0 51 macro
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| D | exynos5250.h | 110 #define CLK_SPI0 304 macro
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| D | exynos5420.h | 80 #define CLK_SPI0 271 macro
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| D | s5pv210.h | 168 #define CLK_SPI0 147 macro
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| D | exynos4.h | 167 #define CLK_SPI0 327 macro
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| D | exynos3250.h | 210 #define CLK_SPI0 206 macro
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| D | exynos4415.h | 273 #define CLK_SPI0 278 macro
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| /linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/ |
| D | pistachio-clk.h | 45 #define CLK_SPI0 51 macro
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| D | exynos5250.h | 110 #define CLK_SPI0 304 macro
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| D | exynos5420.h | 80 #define CLK_SPI0 271 macro
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| D | s5pv210.h | 168 #define CLK_SPI0 147 macro
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| D | exynos4.h | 167 #define CLK_SPI0 327 macro
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| D | exynos3250.h | 210 #define CLK_SPI0 206 macro
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| D | exynos4415.h | 273 #define CLK_SPI0 278 macro
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| /linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/ |
| D | pistachio-clk.h | 45 #define CLK_SPI0 51 macro
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| D | exynos5250.h | 110 #define CLK_SPI0 304 macro
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| D | exynos5420.h | 80 #define CLK_SPI0 271 macro
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| D | s5pv210.h | 168 #define CLK_SPI0 147 macro
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| D | exynos4.h | 167 #define CLK_SPI0 327 macro
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| D | exynos3250.h | 210 #define CLK_SPI0 206 macro
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| D | exynos4415.h | 273 #define CLK_SPI0 278 macro
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| /linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| D | pistachio-clk.h | 45 #define CLK_SPI0 51 macro
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| D | exynos5250.h | 110 #define CLK_SPI0 304 macro
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| D | exynos5420.h | 80 #define CLK_SPI0 271 macro
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| D | s5pv210.h | 168 #define CLK_SPI0 147 macro
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| D | exynos4.h | 167 #define CLK_SPI0 327 macro
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| D | exynos3250.h | 210 #define CLK_SPI0 206 macro
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| D | exynos4415.h | 273 #define CLK_SPI0 278 macro
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| /linux-4.4.14/drivers/clk/pistachio/ |
| D | clk-pistachio.c | 41 GATE(CLK_SPI0, "spi0", "spi0_div", 0x104, 19),
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| /linux-4.4.14/drivers/clk/samsung/ |
| D | clk-exynos5250.c | 633 GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
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| D | clk-s5pv210.c | 620 GATE(CLK_SPI0, "spi0", "dout_pclkp", CLK_GATE_IP3, 12, 0, 0),
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| D | clk-exynos4415.c | 843 GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
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| D | clk-exynos3250.c | 643 GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
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| D | clk-exynos5420.c | 1055 GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
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| D | clk-exynos4.c | 1009 GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16,
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| /linux-4.4.14/arch/arm/boot/dts/ |
| D | exynos3250.dtsi | 566 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
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| D | s5pv210.dtsi | 168 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
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| D | exynos4415.dtsi | 572 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
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| D | exynos4.dtsi | 600 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
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| D | exynos5250.dtsi | 461 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
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| D | exynos5420.dtsi | 460 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
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