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Searched refs:CLK_TOP_APLL1_DIV4 (Results 1 – 8 of 8) sorted by relevance

/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
Dmt8173-clk.h143 #define CLK_TOP_APLL1_DIV4 125 macro
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
Dmt8173-clk.h143 #define CLK_TOP_APLL1_DIV4 125 macro
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
Dmt8173-clk.h143 #define CLK_TOP_APLL1_DIV4 125 macro
/linux-4.4.14/include/dt-bindings/clock/
Dmt8173-clk.h143 #define CLK_TOP_APLL1_DIV4 125 macro
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
Dmt8173-clk.h143 #define CLK_TOP_APLL1_DIV4 125 macro
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
Dmt8173-clk.h143 #define CLK_TOP_APLL1_DIV4 125 macro
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
Dmt8173-clk.h143 #define CLK_TOP_APLL1_DIV4 125 macro
/linux-4.4.14/drivers/clk/mediatek/
Dclk-mt8173.c584 DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24),